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MC68HC05B4 MC68HC705B5 MC68HC05B5 MC68HC05B6 MC68HC05B8 MC68HC05B16 MC68HC705B16 MC68HC705B16N MC68HC05B32 MC68HC705B32
Technical Data
M68HC05 Microcontrollers
MC68HC05B6/D Rev. 4.1 08/2005
freescale.com
INTRODUCTION MODES OF OPERATION AND PIN DESCRIPTIONS MEMORY AND REGISTERS INPUT/OUTPUT PORTS PROGRAMMABLE TIMER SERIAL COMMUNICATIONS INTERFACE PULSE LENGTH D/A CONVERTERS ANALOG TO DIGITAL CONVERTER RESETS AND INTERRUPTS CPU CORE AND INSTRUCTION SET ELECTRICAL SPECIFICATIONS MECHANICAL DATA ORDERING INFORMATION APPENDICES HIGH SPEED OPERATION
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INTRODUCTION MODES OF OPERATION AND PIN DESCRIPTIONS MEMORY AND REGISTERS INPUT/OUTPUT PORTS PROGRAMMABLE TIMER SERIAL COMMUNICATIONS INTERFACE PULSE LENGTH D/A CONVERTERS ANALOG TO DIGITAL CONVERTER RESETS AND INTERRUPTS CPU CORE AND INSTRUCTION SET ELECTRICAL SPECIFICATIONS MECHANICAL DATA ORDERING INFORMATION APPENDICES HIGH SPEED OPERATION
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5. Is the level of technical detail in the following sections sufficient to allow you to understand how the device functions? Too little detail SECTION 1 INTRODUCTION SECTION 2 MODES OF OPERATION AND PIN DESCRIPTIONS SECTION 3 MEMORY AND REGISTERS SECTION 4 INPUT/OUTPUT PORTS SECTION 5 PROGRAMMABLE TIMER SECTION 6 SERIAL COMMUNICATIONS INTERFACE SECTION 7 PULSE LENGTH D/A CONVERTERS SECTION 8 ANALOG TO DIGITAL CONVERTER SECTION 9 RESETS AND INTERRUPTS SECTION 10 CPU CORE AND INSTRUCTION SET SECTION 11 ELECTRICAL SPECIFICATIONS SECTION 12 MECHANICAL DATA SECTION 13 ORDERING INFORMATION SECTION 14 APPENDICES SECTION 15 HIGH SPEED OPERATION Comments: 6. Have you found any errors? If so, please comment: Too much detail

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MC68HC05B6
High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
All Trade Marks recognized. This document contains information on new products. Specifications and information herein are subject to change without notice.
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Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Freescale data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale was negligent regarding the design or manufacture of the part. Freescale, Inc. is an Equal Opportunity/Affirmative Action Employer. The Customer should ensure that it has the most up to date version of the document by contacting its local Freescale office. This document supersedes any earlier documentation relating to the products referred to herein. The information contained in this document is current at the date of publication. It may subsequently be updated, revised or withdrawn.
Freescale LTD., 2005
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Conventions
Where abbreviations are used in the text, an explanation can be found in the glossary, at the back of this manual. Register and bit mnemonics are defined in the paragraphs describing them. An overbar is used to designate an active-low signal, eg: RESET. Unless otherwise stated, shaded cells in a register diagram indicate that the bit is either unused or reserved; `u' is used to indicate an undefined state (on reset). Unless otherwise stated, pins labelled "NU" should be tied to VSS in an electrically noisy environment. Pins labelled "NC" can be left floating, since they are not bonded to any part of the device.
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TABLE OF CONTENTS
Paragraph Number TITLE Page Number
1 INTRODUCTION
1.1 1.2 Features.............................................................................................................1-2 Mask options for the MC68HC05B6 ..................................................................1-3
2 MODES OF OPERATION AND PIN DESCRIPTIONS
2.1 Modes of operation ............................................................................................2-1 2.1.1 Single chip mode .........................................................................................2-1 2.2 Serial RAM loader .............................................................................................2-2 2.3 `Jump to any address'........................................................................................2-4 2.4 Low power modes..............................................................................................2-6 2.4.1 STOP ...........................................................................................................2-6 2.4.2 WAIT ............................................................................................................2-8 2.4.2.1 Power consumption during WAIT mode .................................................2-8 2.4.3 SLOW mode.................................................................................................2-9 2.4.3.1 Miscellaneous register...........................................................................2-9 2.5 Pin descriptions ..............................................................................................2-10 2.5.1 VDD and VSS ............................................................................................2-10 2.5.2 IRQ ............................................................................................................2-10 2.5.3 RESET .......................................................................................................2-10 2.5.4 TCAP1 .......................................................................................................2-10 2.5.5 TCAP2 .......................................................................................................2-11 2.5.6 TCMP1.......................................................................................................2-11 2.5.7 TCMP2.......................................................................................................2-11 2.5.8 OSC1, OSC2 .............................................................................................2-11 2.5.8.1 Crystal ..................................................................................................2-11 2.5.8.2 Ceramic resonator................................................................................2-11 2.5.8.3 External clock .......................................................................................2-12 2.5.9 RDI (Receive data in).................................................................................2-13 2.5.10 TDO (Transmit data out) ............................................................................2-13 2.5.11 SCLK..........................................................................................................2-13 2.5.12 PLMA .........................................................................................................2-13
MC68HC05B6 Rev. 4.1
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Paragraph Number 2.5.13 2.5.14 2.5.15 2.5.16 2.5.17 2.5.18
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PLMB ......................................................................................................... 2-13 VPP1.......................................................................................................... 2-13 VRH ........................................................................................................... 2-13 VRL............................................................................................................ 2-13 PA0 - PA7/PB0 - PB7/PC0 - PC7 ............................................................ 2-13 PD0/AN0-PD7/AN7................................................................................... 2-13
3 MEMORY AND REGISTERS
3.1 3.2 3.3 3.4 3.5 3.5.1 3.5.2 3.5.3 3.5.4 3.5.5 3.6 3.7 3.8 Registers ........................................................................................................... 3-1 RAM .................................................................................................................. 3-1 ROM .................................................................................................................. 3-1 Self-check ROM ................................................................................................ 3-2 EEPROM ........................................................................................................... 3-3 EEPROM control register ............................................................................ 3-3 EEPROM read operation ............................................................................. 3-5 EEPROM erase operation ........................................................................... 3-5 EEPROM programming operation ............................................................... 3-6 Options register (OPTR) .............................................................................. 3-6 EEPROM during STOP mode ........................................................................... 3-7 EEPROM during WAIT mode ............................................................................ 3-7 Miscellaneous register...................................................................................... 3-9
4 INPUT/OUTPUT PORTS
4.1 Input/output programming ................................................................................. 4-1 4.2 Ports A and B .................................................................................................... 4-2 4.3 Port C ................................................................................................................ 4-3 4.4 Port D ................................................................................................................ 4-3 4.5 Port registers ..................................................................................................... 4-4 4.5.1 Port data registers A and B (PORTA and PORTB) ...................................... 4-4 4.5.2 Port data register C (PORTC)...................................................................... 4-4 4.5.3 Port data register D (PORTD)...................................................................... 4-5 4.5.3.1 A/D status/control register...................................................................... 4-5 4.5.4 Data direction registers (DDRA, DDRB and DDRC).................................... 4-5 4.6 Other port considerations .................................................................................. 4-6
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MC68HC05B6 Rev. 4.1
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5 PROGRAMMABLE TIMER
5.1 5.1.1 5.2 5.2.1 5.2.2 5.3 5.3.1 5.3.2 5.4 5.4.1 5.4.2 5.4.3 5.5 5.5.1 5.6 5.7 5.8 Counter ..............................................................................................................5-1 Counter register and alternate counter register ...........................................5-3 Timer control and status ....................................................................................5-4 Timer control register (TCR) ........................................................................5-4 Timer status register (TSR)..........................................................................5-6 Input capture......................................................................................................5-7 Input capture register 1 (ICR1) ....................................................................5-7 Input capture register 2 (ICR2) ....................................................................5-8 Output compare .................................................................................................5-9 Output compare register 1 (OCR1)..............................................................5-9 Output compare register 2 (OCR2)............................................................5-10 Software force compare .............................................................................5-11 Pulse Length Modulation (PLM) ......................................................................5-11 Pulse length modulation registers A and B (PLMA/PLMB) ........................5-11 Timer during STOP mode................................................................................5-12 Timer during WAIT mode.................................................................................5-12 Timer state diagrams .......................................................................................5-12
6 SERIAL COMMUNICATIONS INTERFACE
6.1 6.2 6.3 6.4 6.5 6.6 6.6.1 6.6.2 6.7 6.8 6.9 6.10 6.11 6.11.1 6.11.2 6.11.3 6.11.4 6.11.5 6.12 6.13 6.14 SCI two-wire system features ............................................................................6-1 SCI receiver features .........................................................................................6-3 SCI transmitter features.....................................................................................6-3 Functional description........................................................................................6-3 Data format ........................................................................................................6-5 Receiver wake-up operation ..............................................................................6-5 Idle line wake-up ..........................................................................................6-6 Address mark wake-up ................................................................................6-6 Receive data in (RDI) ........................................................................................6-6 Start bit detection...............................................................................................6-6 Transmit data out (TDO) ....................................................................................6-8 SCI synchronous transmission ..........................................................................6-9 SCI registers ....................................................................................................6-10 Serial communications data register (SCDR) ............................................6-10 Serial communications control register 1 (SCCR1) ...................................6-10 Serial communications control register 2 (SCCR2) ...................................6-14 Serial communications status register (SCSR)..........................................6-16 Baud rate register (BAUD) .........................................................................6-18 Baud rate selection ..........................................................................................6-19 SCI during STOP mode ...................................................................................6-21 SCI during WAIT mode....................................................................................6-21
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7 PULSE LENGTH D/A CONVERTERS
7.1 7.2 7.3 7.4 Miscellaneous register....................................................................................... 7-3 PLM clock selection........................................................................................... 7-4 PLM during STOP mode ................................................................................... 7-4 PLM during WAIT mode .................................................................................... 7-4
8 ANALOG TO DIGITAL CONVERTER
8.1 8.2 8.2.1 8.2.2 8.2.3 8.3 8.4 8.5 A/D converter operation..................................................................................... 8-1 A/D registers...................................................................................................... 8-3 Port D data register (PORTD)...................................................................... 8-3 A/D result data register (ADDATA) ............................................................... 8-3 A/D status/control register (ADSTAT)........................................................... 8-4 A/D converter during STOP mode..................................................................... 8-6 A/D converter during WAIT mode...................................................................... 8-6 Port D analog input............................................................................................ 8-6
9 RESETS AND INTERRUPTS
9.1 Resets ............................................................................................................... 9-1 9.1.1 Power-on reset............................................................................................. 9-2 9.1.2 Miscellaneous register ................................................................................ 9-2 9.1.3 RESET pin ................................................................................................... 9-3 9.1.4 Computer operating properly (COP) watchdog reset .................................. 9-3 9.1.4.1 COP watchdog during STOP mode ....................................................... 9-4 9.1.4.2 COP watchdog during WAIT mode ........................................................ 9-4 9.1.5 Functions affected by reset.......................................................................... 9-5 9.2 Interrupts ........................................................................................................... 9-6 9.2.1 Interrupt priorities......................................................................................... 9-6 9.2.2 Nonmaskable software interrupt (SWI) ........................................................ 9-6 9.2.3 Maskable hardware interrupts ..................................................................... 9-7 9.2.3.1 External interrupt (IRQ).......................................................................... 9-7 9.2.3.2 Miscellaneous register .......................................................................... 9-9 9.2.3.3 Timer interrupts .................................................................................... 9-10 9.2.3.4 Serial communications interface (SCI) interrupts................................. 9-10 9.2.4 Hardware controlled interrupt sequence.................................................... 9-11
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MC68HC05B6 Rev. 4.1
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10 CPU CORE AND INSTRUCTION SET
10.1 Registers .........................................................................................................10-1 10.1.1 Accumulator (A) .........................................................................................10-2 10.1.2 Index register (X)........................................................................................10-2 10.1.3 Program counter (PC) ................................................................................10-2 10.1.4 Stack pointer (SP) ......................................................................................10-2 10.1.5 Condition code register (CCR)...................................................................10-2 10.2 Instruction set ..................................................................................................10-3 10.2.1 Register/memory Instructions ....................................................................10-4 10.2.2 Branch instructions ....................................................................................10-4 10.2.3 Bit manipulation instructions ......................................................................10-4 10.2.4 Read/modify/write instructions ...................................................................10-4 10.2.5 Control instructions ....................................................................................10-4 10.2.6 Tables.........................................................................................................10-4 10.3 Addressing modes .........................................................................................10-11 10.3.1 Inherent....................................................................................................10-11 10.3.2 Immediate ................................................................................................10-11 10.3.3 Direct........................................................................................................10-11 10.3.4 Extended..................................................................................................10-12 10.3.5 Indexed, no offset.....................................................................................10-12 10.3.6 Indexed, 8-bit offset..................................................................................10-12 10.3.7 Indexed, 16-bit offset................................................................................10-12 10.3.8 Relative ....................................................................................................10-13 10.3.9 Bit set/clear ..............................................................................................10-13 10.3.10 Bit test and branch ...................................................................................10-13
11 ELECTRICAL SPECIFICATIONS
11.1 11.2 11.2.1 11.2.2 11.3 11.4 Absolute maximum ratings ..............................................................................11-1 DC electrical characteristics ............................................................................11-2 IDD trends for 5V operation ........................................................................11-3 IDD trends for 3.3V operation .....................................................................11-6 A/D converter characteristics...........................................................................11-8 Control timing ................................................................................................11-10
12 MECHANICAL DATA
12.1 MC68HC05B family pin configurations ............................................................12-1 12.1.1 52-pin plastic leaded chip carrier (PLCC) ..................................................12-1 12.1.2 64-pin quad flat pack (QFP) .......................................................................12-2
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12.1.3 56-pin shrink dual in line package (SDIP).................................................. 12-3 12.2 MC68HC05B6 mechanical dimensions ........................................................... 12-4 12.2.1 52-pin plastic leaded chip carrier (PLCC) .................................................. 12-4 12.2.2 64-pin quad flat pack (QFP)....................................................................... 12-5 12.2.3 56-pin shrink dual in line package (SDIP).................................................. 12-6
13 ORDERING INFORMATION
13.1 13.2 13.3 EPROMS ......................................................................................................... 13-2 Verification media ............................................................................................ 13-2 ROM verification units (RVU)........................................................................... 13-2
A MC68HC05B4
A.1 A.2 Features ........................................................................................................... A-1 Self-check mode............................................................................................... A-5
B MC68HC05B8
B.1 Features ........................................................................................................... B-1
C MC68HC705B5
C.1 C.2 C.2.1 C.3 C.3.1 C.4 C.5 C.5.1 C.5.2 C.5.3 C.5.4 C.5.5 C.6 C.7 Features ........................................................................................................... C-1 EPROM ............................................................................................................ C-5 EPROM programming operation................................................................. C-5 EPROM registers.............................................................................................. C-6 EPROM control register .............................................................................. C-6 Options register (OPTR)................................................................................... C-7 Bootstrap mode ................................................................................................ C-8 Erased EPROM verification ...................................................................... C-11 EPROM parallel bootstrap load ................................................................ C-11 EPROM (RAM) serial bootstrap load and execute ................................... C-13 RAM parallel bootstrap load and execute ................................................. C-14 Bootstrap loader timing diagrams ............................................................. C-17 DC electrical characteristics ........................................................................... C-19 Control timing ................................................................................................. C-19
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MC68HC05B6 Rev. 4.1
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D MC68HC05B16
D.1 D.2 D.3 Features............................................................................................................ D-1 Self-check routines ........................................................................................... D-2 External clock ................................................................................................... D-4
E MC68HC705B16
E.1 Features............................................................................................................ E-2 E.2 External clock ................................................................................................... E-5 E.3 EPROM............................................................................................................. E-5 E.3.1 EPROM read operation............................................................................... E-5 E.3.2 EPROM program operation......................................................................... E-5 E.3.3 EPROM/EEPROM/ECLK control register ................................................... E-6 E.3.4 Mask option register.................................................................................... E-8 E.3.5 EEPROM options register (OPTR) ............................................................. E-9 E.4 Bootstrap mode .............................................................................................. E-10 E.4.1 Erased EPROM verification ...................................................................... E-13 E.4.2 EPROM/EEPROM parallel bootstrap........................................................ E-13 E.4.3 EEPROM/EPROM/RAM serial bootstrap.................................................. E-16 E.4.4 RAM parallel bootstrap ............................................................................. E-19 E.4.4.1 Jump to start of RAM ($0050) ............................................................. E-20 E.5 Absolute maximum ratings ............................................................................. E-21 E.6 DC electrical characteristics ........................................................................... E-22 E.7 A/D converter characteristics.......................................................................... E-24 E.8 Control timing ................................................................................................. E-26 E.9 EPROM electrical characteristics ................................................................... E-28
F MC68HC705B16N
F.1 F.2 F.3 F.4 F.4.1 F.4.2 F.4.3 F.4.4 F.4.5 F.5 F.5.1 Features............................................................................................................ F-2 External clock ................................................................................................... F-5 RESET pin........................................................................................................ F-5 EPROM............................................................................................................. F-5 EPROM read operation............................................................................... F-5 EPROM program operation......................................................................... F-6 EPROM/EEPROM/ECLK control register ................................................... F-6 Mask option register.................................................................................... F-8 EEPROM options register (OPTR) ............................................................. F-9 Bootstrap mode .............................................................................................. F-10 Erased EPROM verification ...................................................................... F-13
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F.5.2 EPROM/EEPROM parallel bootstrap.........................................................F-13 F.5.3 Serial RAM loader......................................................................................F-16 F.5.3.1 Jump to start of RAM ($0051) ..............................................................F-16 F.6 Absolute maximum ratings ..............................................................................F-19 F.7 DC electrical characteristics ............................................................................F-20 F.8 A/D converter characteristics ..........................................................................F-22 F.9 Control timing ..................................................................................................F-24 F.10 EPROM electrical characteristics ....................................................................F-26
G MC68HC05B32
G.1 G.2 Features ........................................................................................................... G-1 External clock ................................................................................................... G-2
H MC68HC705B32
H.1 Features ........................................................................................................... H-3 H.2 External clock ................................................................................................... H-7 H.3 RESET pin........................................................................................................ H-7 H.4 EPROM ............................................................................................................ H-7 H.4.1 EPROM read operation............................................................................... H-8 H.4.2 EPROM program operation ........................................................................ H-8 H.4.3 EPROM/EEPROM control register ............................................................. H-8 H.4.4 Mask option register ................................................................................. H-11 H.4.5 Options register (OPTR) ........................................................................... H-12 H.5 Bootstrap mode .............................................................................................. H-13 H.5.1 Erased EPROM verification ...................................................................... H-16 H.5.2 EPROM/EEPROM parallel bootstrap........................................................ H-16 H.5.3 Serial RAM loader..................................................................................... H-19 H.5.3.1 Jump to start of RAM ($0051) ............................................................. H-19 H.6 Absolute maximum ratings ............................................................................. H-22 H.7 DC electrical characteristics ........................................................................... H-23 H.8 A/D converter characteristics ......................................................................... H-25 H.9 Control timing ................................................................................................. H-27 H.10 EPROM electrical characteristics ................................................................... H-29
I HIGH SPEED OPERATION
I.1 I.2 I.3 DC electrical characteristics ............................................................................... I-2 A/D converter characteristics ............................................................................. I-3 Control timing for 5V operation...........................................................................I-4
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MC68HC05B6 Rev. 4.1
LIST OF FIGURES
Figure Number 1-1 2-1 2-2 2-3 2-4 2-5 3-1 4-1 4-2 4-3 5-1 5-2 5-3 5-4 5-5 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 7-1 7-2 7-3 8-1 8-2 9-1 9-2 9-3 TITLE Page Number
MC68HC05B6 block diagram ............................................................................. 1-3 MC68HC05B6 `load program in RAM and execute' schematic diagram ............ 2-3 MC68HC05B6 `jump to any address' schematic diagram .................................. 2-5 STOP and WAIT flowcharts................................................................................ 2-7 Slow mode divider block diagram ....................................................................... 2-9 Oscillator connections ...................................................................................... 2-12 Memory map of the MC68HC05B6 .................................................................... 3-2 Standard I/O port structure................................................................................. 4-2 ECLK timing diagram.......................................................................................... 4-3 Port logic levels................................................................................................... 4-6 16-bit programmable timer block diagram .......................................................... 5-2 Timer state timing diagram for reset ................................................................. 5-13 Timer state timing diagram for input capture .................................................... 5-13 Timer state timing diagram for output compare ................................................ 5-14 Timer state timing diagram for timer overflow................................................... 5-14 Serial communications interface block diagram ................................................. 6-2 SCI rate generator division ................................................................................. 6-4 Data format......................................................................................................... 6-5 SCI examples of start bit sampling technique .................................................... 6-7 SCI sampling technique used on all bits............................................................. 6-7 Artificial start following a framing error ............................................................... 6-8 SCI start bit following a break............................................................................. 6-8 SCI example of synchronous and asynchronous transmission .......................... 6-9 SCI data clock timing diagram (M=0) ............................................................... 6-12 SCI data clock timing diagram (M=1) ............................................................... 6-13 PLM system block diagram................................................................................. 7-1 PLM output waveform examples ........................................................................ 7-2 PLM clock selection............................................................................................ 7-4 A/D converter block diagram .............................................................................. 8-2 Electrical model of an A/D input pin ................................................................... 8-6 Reset timing diagram.......................................................................................... 9-1 Watchdog system block diagram ........................................................................ 9-3 Interrupt flow chart.............................................................................................. 9-8
MC68HC05B6 Rev. 4.1
LIST OF FIGURES
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Figure Number 10-1 10-2 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 12-1 12-2 12-3 12-4 12-5 12-6 A-1 A-2 A-3 B-1 B-2 C-1 C-2 C-3 C-4 C-5 C-6 C-7 C-8 C-9 C-10 D-1 D-2 D-3 E-1 E-2 E-3
TITLE
Page Number
Programming model ......................................................................................... 10-1 Stacking order .................................................................................................. 10-1 Run IDD vs internal operating frequency (4.5V, 5.5V) ...................................... 11-3 Run IDD (SM = 1) vs internal operating frequency (4.5V, 5.5V) ....................... 11-3 Wait IDD vs internal operating frequency (4.5V, 5.5V)...................................... 11-3 Wait IDD (SM = 1) vs internal operating frequency (4.5V, 5.5V)....................... 11-4 Increase in IDD vs frequency for A/D, SCI systems active, VDD = 5.5V........... 11-4 IDD vs mode vs internal operating frequency, VDD = 5.5V ............................... 11-4 Run IDD vs internal operating frequency (3 V, 3.6V)......................................... 11-6 Run IDD (SM = 1) vs internal operating frequency (3V,3.6V) ........................... 11-6 Wait IDD vs internal operating frequency (3V, 3.6V)......................................... 11-6 Wait IDD (SM = 1) vs internal operating frequency (3V, 3.6V).......................... 11-7 Increase in IDD vs frequency for A/D, SCI systems active, VDD = 3.6V............ 11-7 IDD vs mode vs internal operating frequency, VDD = 3.6V ............................... 11-7 Timer relationship........................................................................................... 11-12 52-pin PLCC pinout for the MC68HC05B6....................................................... 12-1 64-pin QFP pinout for the MC68HC05B6......................................................... 12-2 56-pin SDIP pinout for the MC68HC05B6........................................................ 12-3 52-pin PLCC mechanical dimensions .............................................................. 12-4 64-pin QFP mechanical dimensions................................................................. 12-5 56-pin SDIP mechanical dimensions................................................................ 12-6 MC68HC05B4 block diagram .............................................................................A-2 Memory map of the MC68HC05B4 ....................................................................A-3 MC68HC05B4 self-check schematic diagram ....................................................A-7 MC68HC05B8 block diagram .............................................................................B-2 Memory map of the MC68HC05B8 ....................................................................B-3 MC68HC705B5 block diagram ...........................................................................C-2 Memory map of the MC68HC705B5 ..................................................................C-3 Modes of operation flow chart (1 of 2)................................................................C-9 Modes of operation flow chart (2 of 2)..............................................................C-10 Timing diagram with handshake.......................................................................C-11 EPROM(RAM) parallel bootstrap schematic diagram ......................................C-12 EPROM (RAM) serial bootstrap schematic diagram ........................................C-15 RAM parallel bootstrap schematic diagram......................................................C-16 EPROM parallel bootstrap loader timing diagram ............................................C-17 RAM parallel loader timing diagram ................................................................C-18 MC68HC05B16 block diagram ...........................................................................D-3 Oscillator connections ........................................................................................D-4 Memory map of the MC68HC05B16 ..................................................................D-5 MC68HC705B16 block diagram .........................................................................E-2 Memory map of the MC68HC705B16 ................................................................E-3 Modes of operation flow chart (1 of 2)..............................................................E-11
Freescale x
LIST OF FIGURES
MC68HC05B6 Rev. 4.1
Figure Number E-4 E-5 E-6 E-7 E-8 E-9 E-10 E-11 F-1 F-2 F-3 F-4 F-5 F-6 F-7 F-8 F-9 F-10 G-1 G-2 H-1 H-2 H-3 H-4 H-5 H-6 H-7 H-8 H-9 H-10 I-1
TITLE
Page Number
Modes of operation flow chart (2 of 2) ..............................................................E-12 Timing diagram with handshake .......................................................................E-14 Parallel EPROM loader timing diagram ............................................................E-14 EPROM Parallel bootstrap schematic diagram.................................................E-15 RAM/EPROM/EEPROM serial bootstrap schematic diagram ..........................E-17 Parallel RAM loader timing diagram .................................................................E-19 RAM parallel bootstrap schematic diagram ......................................................E-20 Timer relationship .............................................................................................E-28 MC68HC705B16N block diagram.......................................................................F-2 Memory map of the MC68HC705B16N..............................................................F-3 Modes of operation flow chart (1 of 2) ..............................................................F-11 Modes of operation flow chart (2 of 2) ..............................................................F-12 Timing diagram with handshake .......................................................................F-14 Parallel EPROM loader timing diagram ............................................................F-14 EPROM parallel bootstrap schematic diagram.................................................F-15 RAM load and execute schematic diagram ......................................................F-17 Parallel RAM loader timing diagram .................................................................F-18 Timer relationship .............................................................................................F-26 MC68HC05B32 block diagram .......................................................................... G-2 Memory map of the MC68HC05B32 ................................................................. G-3 MC68HC705B32 block diagram ........................................................................ H-4 Memory map of the MC68HC705B32 ............................................................... H-5 Modes of operation flow chart (1 of 2) ............................................................. H-14 Modes of operation flow chart (2 of 2) ............................................................. H-15 Timing diagram with handshake ...................................................................... H-17 Parallel EPROM loader timing diagram ........................................................... H-17 EPROM parallel bootstrap schematic diagram................................................ H-18 RAM load and execute schematic diagram ..................................................... H-20 Parallel RAM loader timing diagram ................................................................ H-21 Timer relationship ............................................................................................ H-29 Timer relationship ................................................................................................ I-5
MC68HC05B6 Rev. 4.1
LIST OF FIGURES
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Freescale xii
LIST OF FIGURES
MC68HC05B6 Rev. 4.1
LIST OF TABLES
Table Number 1-1 2-1 3-1 3-2 3-3 4-1 6-1 6-2 6-3 6-4 6-5 6-6 8-1 8-2 9-1 9-2 9-3 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 11-1 11-2 11-3 11-4 11-5 11-6 11-7 TITLE Page Number
Data sheet appendices....................................................................................... 1-1 Mode of operation selection ............................................................................... 2-1 EEPROM control bits description ....................................................................... 3-4 Register outline................................................................................................... 3-8 IRQ sensitivity..................................................................................................... 3-9 I/O pin states ...................................................................................................... 4-2 Method of receiver wake-up ............................................................................. 6-11 SCI clock on SCLK pin ..................................................................................... 6-13 First prescaler stage ......................................................................................... 6-18 Second prescaler stage (transmitter) ............................................................... 6-18 Second prescaler stage (receiver).................................................................... 6-19 SCI baud rate selection .................................................................................... 6-20 A/D clock selection ............................................................................................. 8-4 A/D channel assignment..................................................................................... 8-5 Effect of RESET, POR, STOP and WAIT............................................................ 9-5 Interrupt priorities ............................................................................................... 9-7 IRQ sensitivity..................................................................................................... 9-9 MUL instruction ................................................................................................ 10-5 Register/memory instructions........................................................................... 10-5 Branch instructions ........................................................................................... 10-6 Bit manipulation instructions............................................................................. 10-6 Read/modify/write instructions ......................................................................... 10-7 Control instructions........................................................................................... 10-7 Instruction set (1 of 2)....................................................................................... 10-8 Instruction set (2 of 2)....................................................................................... 10-9 M68HC05 opcode map................................................................................... 10-10 Absolute maximum ratings ............................................................................... 11-1 DC electrical characteristics for 5V operation................................................... 11-2 DC electrical characteristics for 3.3V operation................................................ 11-5 A/D characteristics for 5V operation ................................................................. 11-8 A/D characteristics for 3.3V operation .............................................................. 11-9 Control timing for 5V operation ....................................................................... 11-10 Control timing for 3.3V operation .................................................................... 11-11
MC68HC05B6 Rev. 4.1
LIST OF TABLES
Freescale xiii
Table Number 13-1 13-2 A-1 A-2 A-3 B-1 C-1 C-2 C-3 C-4 C-5 D-1 D-2 E-1 E-2 E-3 E-4 E-5 E-6 E-7 E-8 E-9 E-10 E-11 E-12 E-13 E-14 E-15 F-1 F-2 F-3 F-4 F-5 F-6 F-7 F-8 F-9 F-10 F-11 F-12 F-13 F-14
TITLE
Page Number
MC order numbers ........................................................................................... 13-1 EPROMs for pattern generation ....................................................................... 13-2 Mode of operation selection ...............................................................................A-1 Register outline ..................................................................................................A-4 MC68HC05B4 self-check results .......................................................................A-6 Register outline ..................................................................................................B-4 Register outline ..................................................................................................C-4 Mode of operation selection ...............................................................................C-8 Bootstrap vector targets in RAM ......................................................................C-14 Additional DC electrical characteristics for MC68HC705B5.............................C-19 Additional control timing for MC68HC705B5 ....................................................C-19 Mode of operation selection ...............................................................................D-2 Register outline ..................................................................................................D-6 Register outline ..................................................................................................E-4 EPROM control bits description .........................................................................E-6 EEPROM control bits description .......................................................................E-7 Mode of operation selection .............................................................................E-10 Bootstrap vector targets in RAM ......................................................................E-18 Absolute maximum ratings ...............................................................................E-21 DC electrical characteristics for 5V operation ..................................................E-22 DC electrical characteristics for 3.3V operation ...............................................E-23 A/D characteristics for 5V operation.................................................................E-24 A/D characteristics for 3.3V operation..............................................................E-25 Control timing for 5V operation.........................................................................E-26 Control timing for 3.3V operation......................................................................E-27 DC electrical characteristics for 5V operation ..................................................E-28 Control timing for 5V operation.........................................................................E-28 Control timing for 3.3V operation......................................................................E-28 Register outline .................................................................................................. F-4 EPROM control bits description ......................................................................... F-7 EEPROM control bits description ....................................................................... F-8 Mode of operation selection ............................................................................. F-10 Bootstrap vector targets in RAM ...................................................................... F-16 Absolute maximum ratings ............................................................................... F-19 DC electrical characteristics for 5V operation .................................................. F-20 DC electrical characteristics for 3.3V operation ............................................... F-21 A/D characteristics for 5V operation................................................................. F-22 A/D characteristics for 3.3V operation.............................................................. F-23 Control timing for 5V operation......................................................................... F-24 Control timing for 3.3V operation...................................................................... F-25 DC electrical characteristics for 5V operation .................................................. F-26 Control timing for 5V operation......................................................................... F-26
Freescale xiv
LIST OF TABLES
MC68HC05B6 Rev. 4.1
Table Number F-15 G-1 H-1 H-2 H-3 H-4 H-5 H-6 H-7 H-8 H-9 H-10 H-11 H-12 H-13 H-14 H-15 I-1 I-2 I-3
TITLE
Page Number
Control timing for 3.3V operation ......................................................................F-26 Register outline.................................................................................................. G-4 Register outline.................................................................................................. H-6 EPROM control bits description......................................................................... H-9 EEPROM control bits description .................................................................... H-10 Mode of operation selection ............................................................................ H-13 Bootstrap vector targets in RAM...................................................................... H-19 Absolute Maximum ratings .............................................................................. H-22 DC electrical characteristics for 5V operation.................................................. H-23 DC electrical characteristics for 3.3V operation............................................... H-24 A/D characteristics for 5V operation ................................................................ H-25 A/D characteristics for 3.3V operation ............................................................. H-26 Control timing for 5V operation ........................................................................ H-27 Control timing for operation at 3.3V ................................................................. H-28 DC electrical characteristics for 5V operation.................................................. H-29 Control timing for 5V operation ........................................................................ H-29 Control timing for 3.3V operation ..................................................................... H-29 Ordering information............................................................................................ I-1 DC electrical characteristics for 5V operation...................................................... I-2 A/D characteristics for 5V operation .................................................................... I-3
MC68HC05B6 Rev. 4.1
LIST OF TABLES
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LIST OF TABLES
MC68HC05B6 Rev. 4.1
1
1
INTRODUCTION
The MC68HC05B6 microcomputer (MCU) is a member of Freescale's MC68HC05 family of low-cost single chip microcomputers. This 8-bit MCU contains an on-chip oscillator, CPU, RAM, ROM, EEPROM, A/D converter, pulse length modulated outputs, I/O, serial communications interface, programmable timer system and watchdog. The fully static design allows operation at frequencies down to dc to further reduce the already low power consumption to a few micro-amps. This data sheet is structured such that devices similar to the MC68HC05B6 are described in a set of appendices (see Table 1-1).
Table 1-1 Data sheet appendices
Device MC68HC05B4 MC68HC05B8 MC68HC705B5 MC68HC05B16 MC68HC705B16 MC68HC705B16N MC68HC05B32 MC68HC705B32 Appendix A B C D E F G H Differences from MC68HC05B6 4K bytes ROM; no EEPROM 7.25K bytes ROM 6K bytes EPROM; self-check replaced by bootstrap firmware; no EEPROM 16K bytes ROM; increased RAM and self-check ROM 16K bytes EPROM; increased RAM; self-check replaced by bootstrap firmware; modified power-on reset routine 16K bytes EPROM; increased RAM; self-check replaced by bootstrap firmware; modified power-on reset routine 32K bytes ROM; no page zero ROM; increased RAM 32K bytes EPROM; no page zero ROM; increased RAM; self-check mode replaced by bootstrap firmware
MC68HC05B6 Rev. 4.1
INTRODUCTION
Freescale 1-1
1
1.1 Features
Hardware features * * * * * * * * * * * * * * * * * * * * * Fully static design featuring the industry standard M68HC05 family CPU core On chip crystal oscillator with divide by 2 or a software selectable divide by 32 option (SLOW mode) 2.1 MHz internal operating frequency at 5V; 1.0 MHz at 3V High speed version available 176 bytes of RAM 5936 bytes of user ROM plus 14 bytes of user vectors 256 bytes of byte erasable EEPROM with internal charge pump and security bit Write/erase protect bit for 224 of the 256 bytes EEPROM Self test/bootstrap mode Power saving STOP, WAIT and SLOW modes Three 8-bit parallel I/O ports and one 8-bit input-only port Software option available to output the internal E-clock to port pin PC2 16-bit timer with 2 input captures and 2 output compares Computer operating properly (COP) watchdog timer Serial communications interface system (SCI) with independent transmitter/receiver baud rate selection; receiver wake-up function for use in multi-receiver systems 8 channel A/D converter 2 pulse length modulation systems which can be used as D/A converters One interrupt request input plus 4 on-board hardware interrupt sources Available in 52-pin plastic leaded chip carrier (PLCC), 64-pin quad flat pack (QFP) and 56-pin shrink dual in line (SDIP) packages Complete development system support available using the MMDS05 development station with the M68HC05B32EM emulation module Extended operating temperature range of -40 to +125 C
Freescale 1-2
INTRODUCTION
MC68HC05B6 Rev. 4.1
1
1.2 Mask options for the MC68HC05B6
The MC68HC05B6 has three mask options that are programmed during manufacture and must be specified on the order form. * * * Power-on-reset delay (tPORL) = 16 or 4064 cycles Automatic watchdog enable/disable following a power-on or external reset Watchdog enable/disable during WAIT mode
Warning: It is recommended that an external clock is always used if tPORL is set to 16 cycles. This will prevent any problems arising with oscillator stability when the device is put into STOP mode.
VPP1
Charge pump
5950 bytes User ROM (including 14 bytes User vectors)
Port A
256 bytes EEPROM
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2/ECLK PC3 PC4 PC5 PC6 PC7 TCMP1 TCMP2 TCAP1 TCAP2 RDI SCLK TDO PLMA D/A PLMB D/A
RESET IRQ OSC2 OSC1
COP watchdog Port B 432 bytes self check ROM 176 bytes RAM 16-bit programmable timer Port D 8-bit A/D converter SCI PLM
Oscillator
/ 2 / / 32
M68HC05 CPU
VDD VSS
PD0/AN0 PD1/AN1 PD2/AN2 PD3/AN3 PD4/AN4 PD5/AN5 PD6/AN6 PD7/AN7 VRH VRL
Figure 1-1 MC68HC05B6 block diagram
MC68HC05B6 Rev. 4.1
INTRODUCTION
Port C
Freescale 1-3
1
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Freescale 1-4
INTRODUCTION
MC68HC05B6 Rev. 4.1
2
2
MODES OF OPERATION AND PIN DESCRIPTIONS
2.1 Modes of operation
The MC68HC05B6 MCU has two modes of operation, namely single chip and self check modes. Table 2-1 shows the conditions required to enter each mode on the rising edge of RESET.
Table 2-1 Mode of operation selection
IRQ pin VSS to VDD 2VDD 2VDD TCAP1 pin VSS to VDD VDD VDD PD3 X 1 1 PD4 X 0 1 Mode Single chip Serial RAM loader Jump to any address
2.1.1
Single chip mode
This is the normal operating mode of the MC68HC05B6. In this mode the device functions as a self-contained microcomputer (MCU) with all on-board peripherals, including the three 8-bit I/O ports and the 8-bit input-only port, available to the user. All address and data activity occurs within the MCU.
MC68HC05B6 Rev. 4.1
MODES OF OPERATION AND PIN DESCRIPTIONS
Freescale 2-1
2.2
Serial RAM loader
2
The `load program in RAM and execute' mode is entered if the following conditions are satisfied when the reset pin is released to VDD. The format used is identical to the format used for the MC68HC805C4. The SEC bit in the options register must be inactive, i.e. set to `1'. - - - - IRQ at 2xVDD TCAP1 at VDD PD3 at VDD for at least 30 machine cycles after reset PD4 at VSS for at least 30 machine cycles after reset
In the `load program in RAM and execute' routine, user programs are loaded into MCU RAM via the SCI port and then executed. Data is loaded sequentially, starting at RAM location $0050, until the last byte is loaded. Program control is then transferred to the RAM program starting at location $0051. The first byte loaded is the count of the total number of bytes in the program plus the count byte. The program starts at the second byte in RAM. During the firmware initialization stage, the SCI is configured for the NRZ data format (idle line, start bit, eight data bits and stop bit). The baud rate is 9600 with a 4 MHz crystal. A program to convert ASCII S-records to the format required by the RAM loader is available from Freescale. If immediate execution is not desired after loading the RAM program, it is possible to hold off execution. This is accomplished by setting the byte count to a value that is greater than the overall length of the loaded data. When the last byte is loaded, the firmware will halt operation expecting additional data to arrive. At this point, the reset switch is placed in the reset position which will reset the MCU, but keep the RAM program intact. All routines can now be entered from this state, including the one which will execute the program in RAM (see Section 2.3). To load a program in the EEPROM, the `load program in RAM and execute' function is also used. In this instance the process involves two distinct steps. Firstly, the RAM is loaded with a program which will control the loading of the EEPROM, and when the RAM contents are executed, the MCU is instructed to load the EEPROM. The erased state of the EEPROM is $FF. Figure 2-1 shows the schematic diagram of the circuit required for the serial RAM loader.
Freescale 2-2
MODES OF OPERATION AND PIN DESCRIPTIONS
MC68HC05B6 Rev. 4.1
P1 10 nF 10 k RESET 10 VDD OSC1 18 0.01 F 6 15
9600 Bd RS232 level translator suggested: MC145406 or MAX232
47 F
GND +5V 2xVDD
2
16 17 10 M
RESET
OSC2
22 pF NC NC IRQ RDI TDO PD3 PD4 19 11 9 22 8 7 40 20 21 51
4 MHz
22 pF 10 k
50 52
RS232
MC68HC05B6 (52-pin package)
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 42 43 44 45 46 47 48 49
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
TCAP1 VRH VRL VPP1 PLMA PLMB SCLK
Connect as required for the application
TCMP2 TCAP2 TCMP1 PD7 PD6 PD5 PD2 PD1 PD0 VSS 41
1 23 2 3 4 5 12 13 14
Connect as required for the application
Figure 2-1 MC68HC05B6 `load program in RAM and execute' schematic diagram
MC68HC05B6 Rev. 4.1
MODES OF OPERATION AND PIN DESCRIPTIONS
Freescale 2-3
2.3
`Jump to any address'
2
The `jump to any address' mode is entered when the reset pin is released to VDD, if the following conditions are satisfied: - - - - IRQ at 2xVDD TCAP1 at VDD PD3 at VDD for at least 30 machine cycles after reset PD4 at VDD for at least 30 machine cycles after reset
This function allows execution of programs previously loaded in RAM or EEPROM using the methods outlined in Section 2.2. To execute the `jump to any address' function, data input at port A has to be $CC and data input at port B and port C should represent the MSB and LSB respectively, of the address to jump to for execution of the user program. A schematic diagram of the circuit required is shown in Figure 2-2.
Freescale 2-4
MODES OF OPERATION AND PIN DESCRIPTIONS
MC68HC05B6 Rev. 4.1
P1 10 nF 10 k RESET 10 VDD OSC1 18 0.01 F 6 15 22 pF NC NC IRQ 8 x 10 k optional (see note) 24 25 26 27 28 29 30 31 PD3 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PD4 19 11 9 22 8 7 40 20 21 51 50 52 1 23 2 3 4 5 12 13 14 Connect as required for the application 4 MHz 22 pF 10 k RESET OSC2 16 17 10 M 47 F
GND +5V 2xVDD
2
MC68HC05B6 (52-pin package)
TCAP1 VRH VRL VPP1 PLMA PLMB SCLK RDI TDO TCMP2
8 x 10 k
Select required address
32 33 34 35 36 37 38 39
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
MSB
8 x 10 k
42 43 44 45 46 47 48 49
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 VSS 41
TCAP2 TCMP1 PD7 PD6 PD5 PD2 PD1 PD0
Note:
LSB
These eight resistors are optional; direct connection is possible if pins PA0-PA7, PB0-PB7 and PC0-PC7 are kept in input mode during application.
Figure 2-2 MC68HC05B6 `jump to any address' schematic diagram
MC68HC05B6 Rev. 4.1
MODES OF OPERATION AND PIN DESCRIPTIONS
Freescale 2-5
2.4
Low power modes
2
The STOP and WAIT instructions have different effects on the programmable timer, the serial communications interface, the watchdog system, the EEPROM and the A/D converter. These different effects are described in the following sections.
2.4.1
STOP
The STOP instruction places the MCU in its lowest power consumption mode. In STOP mode, the internal oscillator is turned off, halting all internal processing including timer, serial communications interface and the A/D converter (see flowchart in Figure 2-3). The only way for the MCU to wake-up from the STOP mode is by receipt of an external interrupt or by the detection of a reset (logic low on RESET pin or a power-on reset). During STOP mode, the I-bit in the CCR is cleared to enable external interrupts (see Section 10.1.5). The SM bit is cleared to allow nominal speed operation for the 4064 cycles count while exiting STOP mode (see Section 2.4.3). All other registers and memory remain unaltered and all input/output lines remain unchanged. This continues until an external interrupt (IRQ) or reset is sensed, at which time the internal oscillator is turned on. The external interrupt or reset causes the program counter to vector to the corresponding locations ($1FFA, B and $1FFE, F respectively). When leaving STOP mode, a tPORL internal cycles delay is provided to give the oscillator time to stabilise before releasing CPU operation. This delay is selectable via a mask option to be either 16 or 4064 cycles. The CPU will resume operation by servicing the interrupt that wakes it up, or by fetching the reset vector, if reset wakes it up. Warning: If tPORL is selected to be 16 cycles, it is recommended that an external clock signal is used to avoid problems with oscillator stability while the device is in STOP mode. Note: The stacking corresponding to an eventual interrupt to go out of STOP mode will only be executed when going out of STOP mode.
The following list summarizes the effect of STOP mode on the individual modules of the MC68HC05B6. - - - - - - - The watchdog timer is reset; refer to Section 9.1.4.1 The EEPROM acts as read-only memory (ROM); refer to Section 3.6 All SCI activity stopped; refer to Section 6.13 The timer stops counting; refer to Section 5.6 The PLM outputs remain at current level; refer to Section 7.3 The A/D converter is disabled; refer to Section 8.3 The I-bit in the CCR is cleared
Freescale 2-6
MODES OF OPERATION AND PIN DESCRIPTIONS
MC68HC05B6 Rev. 4.1
STOP
WAIT
2
YES
Watchdog active?
NO
Stop oscillator and all clocks. Clear I bit.
Oscillator active. Timer, SCI, A/D, EEPROM clocks active. Processor clocks stopped Clear I-bit
NO
Reset?
Reset?
NO
NO
IRQ external interrupt?
YES
YES
YES
IRQ external interrupt?
YES YES
NO
Timer interrupt?
NO
Turn on oscillator. Wait for time delay to stabilise
YES
SCI interrupt?
NO
Restart processor clock
Generate watchdog reset
(1) Fetch reset vector or (2) Service interrupt: a. stack b. set I-bit c. vector to interrupt routine
(1) Fetch reset vector or (2) Service interrupt: a. stack b. set I-bit c. vector to interrupt routine
Figure 2-3 STOP and WAIT flowcharts
MC68HC05B6 Rev. 4.1
MODES OF OPERATION AND PIN DESCRIPTIONS
Freescale 2-7
2.4.2
WAIT
2
The WAIT instruction places the MCU in a low power consumption mode, but WAIT mode consumes more power than STOP mode. All CPU action is suspended and the watchdog is disabled, but the timer, A/D and SCI systems remain active and operate as normal (see flowchart in Figure 2-3). All other memory and registers remain unaltered and all parallel input/output lines remain unchanged. The programming or erase mechanism of the EEPROM is also unaffected, as well as the charge pump high voltage generator. During WAIT mode the I-bit in the CCR is cleared to enable all interrupts. The INTE bit in the miscellaneous register (Section 2.5) is not affected by WAIT mode. When any interrupt or reset is sensed, the program counter vectors to the locations containing the start address of the interrupt or reset service routine. Any IRQ, timer (overflow, input capture or output compare) or SCI interrupt (in addition to a logic low on the RESET pin) causes the processor to exit WAIT mode. If a non-reset exit from WAIT mode is performed (i.e. timer overflow interrupt exit), the state of the remaining systems will be unchanged. If a reset exit from WAIT mode is performed the entire system reverts to the disabled reset state. Note: The stacking corresponding to an eventual interrupt to leave WAIT mode will only be executed when leaving WAIT mode.
The following list summarizes the effect of WAIT mode on the modules of the MC68HC05B6. - - - - - - - The watchdog timer functions according to the mask option selected; refer to Section 9.1.4.2 The EEPROM is not affected; refer to Section 3.7 The SCI is not affected; refer to Section 6.14 The timer is not affected; refer to Section 5.7 The PLM is not affected; refer to Section 7.4 The A/D converter is not affected; refer to Section 8.4 The I-bit in the CCR is cleared
2.4.2.1
Power consumption during WAIT mode
Power consumption during WAIT mode depends on how many systems are active. The power consumption will be highest when all the systems (A/D, timer, EEPROM and SCI) are active, and lowest when the EEPROM erase and programming mechanism, SCI and A/D are disabled. The timer cannot be disabled in WAIT mode. It is important that before entering WAIT mode, the programmer sets the relevant control bits for the individual modules to reflect the desired functionality during WAIT mode. Power consumption may be further reduced by the use of SLOW mode.
Freescale 2-8
MODES OF OPERATION AND PIN DESCRIPTIONS
MC68HC05B6 Rev. 4.1
2.4.3
SLOW mode
The SLOW mode function is controlled by the SM bit in the miscellaneous register at location $000C. It allows the user to insert, under software control, an extra divide-by-16 between the oscillator and the internal clock driver (see Figure 2-4). This feature permits a slow down of all the internal operations and thus reduces power consumption. The SLOW mode function should not be enabled while using the A/D converter or while erasing/programming the EEPROM unless the internal A/D RC oscillator is turned on.
2
OSC1 pin
OSC2 pin
Oscillator
fOSC
/2
fOSC/2
/ 16
fOSC/32
SM-bit (bit 1, $000C)
Control logic Main internal clock
Figure 2-4 Slow mode divider block diagram
2.4.3.1
Miscellaneous register
Address bit 7 POR bit 6 INTP bit 5 INTN bit 4 INTE bit 3 SFA bit 2 SFB bit 1 SM bit 0 State on reset
Miscellaneous
$000C
WDOG ?001 000?
SM -- Slow mode 1 (set) - The system runs at a bus speed 16 times lower than normal (fOSC/32). SLOW mode affects all sections of the device, including SCI, A/D and timer. The system runs at normal bus speed (fOSC/2).
0 (clear) -
The SM bit is cleared by external or power-on reset. The SM bit is automatically cleared when entering STOP mode. Note: The bits shown shaded in the above representation are explained individually in the relevant sections of this manual. The complete register plus an explanation of each bit can be found in Section 3.8.
MC68HC05B6 Rev. 4.1
MODES OF OPERATION AND PIN DESCRIPTIONS
Freescale 2-9
2.5
Pin descriptions VDD and VSS
2
2.5.1
Power is supplied to the microcontroller using these two pins. VDD is the positive supply and VSS is ground. It is in the nature of CMOS designs that very fast signal transitions occur on the MCU pins. These short rise and fall times place very high short-duration current demands on the power supply. To prevent noise problems, special care must be taken to provide good power supply by-passing at the MCU. By-pass capacitors should have good high-frequency characteristics and be as close to the MCU as possible. Bypassing requirements vary, depending on how heavily the MCU pins are loaded.
2.5.2
IRQ
This is an input-only pin for external interrupt sources. Interrupt triggering is selected using the INTP and INTN bits in the miscellaneous register, to be one of four options detailed in Table 9-3. In addition, the external interrupt facility (IRQ) can be disabled using the INTE bit in the miscellaneous register (see Section 3.8). It is only possible to change the interrupt option bits in the miscellaneous register while the I-bit is set. Selecting a different interrupt option will automatically clear any pending interrupts. Further details of the external interrupt procedure can be found in Section 9.2.3.1. The IRQ pin contains an internal Schmitt trigger as part of its input to improve noise immunity.
2.5.3
RESET
This active low I/O pin is used to reset the MCU. Applying a logic zero to this pin forces the device to a known start-up state. An external RC-circuit can be connected to this pin to generate a power-on-reset (POR) if required. In this case, the time constant must be great enough to allow the oscillator circuit to stabilize. This input has an internal Schmitt trigger to improve noise immunity. When a reset condition occurs internally, i.e. from the COP watchdog, the RESET pin provides an active-low open drain output signal that may be used to reset external hardware.
2.5.4
TCAP1
The TCAP1 input controls the input capture 1 function of the on-chip programmable timer system.
Freescale 2-10
MODES OF OPERATION AND PIN DESCRIPTIONS
MC68HC05B6 Rev. 4.1
2.5.5
TCAP2
The TCAP2 input controls the input capture 2 function of the on-chip programmable timer system.
2
2.5.6
TCMP1
The TCMP1 pin is the output of the output compare 1 function of the timer system.
2.5.7
TCMP2
The TCMP2 pin is the output of the output compare 2 function of the timer system.
2.5.8
OSC1, OSC2
These pins provide control input for an on-chip oscillator circuit. A crystal, ceramic resonator or external clock signal connected to these pins supplies the oscillator clock. The oscillator frequency (fOSC) is divided by two to give the internal bus frequency (fOP). There is also a software option which introduces an additional divide by 16 into the oscillator clock, giving an internal bus frequency of fOSC/32.
2.5.8.1
Crystal
The circuit shown in Figure 2-5(a) is recommended when using either a crystal or a ceramic resonator. Figure 2-5(d) lists the recommended capacitance and feedback resistance values. The internal oscillator is designed to interface with an AT-cut parallel-resonant quartz crystal resonator in the frequency range specified for fOSC (see Section 11.4). Use of an external CMOS oscillator is recommended when crystals outside the specified ranges are to be used. The crystal and associated components should be mounted as close as possible to the input pins to minimise output distortion and start-up stabilisation time. The manufacturer of the particular crystal being considered should be consulted for specific information.
2.5.8.2
Ceramic resonator
A ceramic resonator may be used instead of a crystal in cost sensitive applications. The circuit shown in Figure 2-5(a) is recommended when using either a crystal or a ceramic resonator. Figure 2-5(d) lists the recommended capacitance and feedback resistance values. The manufacturer of the particular ceramic resonator being considered should be consulted for specific information.
MC68HC05B6 Rev. 4.1
MODES OF OPERATION AND PIN DESCRIPTIONS
Freescale 2-11
2.5.8.3
External clock
2
An external clock should be applied to the OSC1 input, with the OSC2 pin left unconnected, as shown in Figure 2-5(c). The tOXOV or tILCH specifications (see Section 11.4) do not apply when using an external clock input. The equivalent specification of the external clock source should be used in lieu of tOXOV or tILCH.
L OSC1 C1 RS OSC2
MCU OSC1 RP OSC2
C0
(b) Crystal equivalent circuit COSC1 COSC2 MCU OSC1 (a) Crystal/ceramic resonator oscillator connections OSC2
External clock
NC
(c) External clock source connections Crystal 2MHz RS(max) C0 C1 COSC1 COSC2 RP Q 400 5 8 4MHz 75 7 12 Unit pF F pF pF M -- RS(typ) C0 C1 COSC1 COSC2 RP Q Ceramic resonator 2 - 4MHz 10 40 4.3 30 30 1 - 10 1250 Unit pF pF pF pF M --
15 - 40 15 - 30 15 - 30 15 - 25 10 30 000 10 40 000
(d) Typical crystal and ceramic resonator parameters
Figure 2-5 Oscillator connections
Freescale 2-12
MODES OF OPERATION AND PIN DESCRIPTIONS
MC68HC05B6 Rev. 4.1
2.5.9
RDI (Receive data in)
The RDI pin is the input pin of the SCI receiver.
2
2.5.10
TDO (Transmit data out)
The TDO pin is the output pin of the SCI transmitter.
2.5.11
SCLK
The SCLK pin is the clock output pin of the SCI transmitter.
2.5.12
PLMA
The PLMA pin is the output of pulse length modulation converter A.
2.5.13
PLMB
The PLMB pin is the output of pulse length modulation converter B.
2.5.14
VPP1
The VPP1 pin is the output of the charge pump for the EEPROM1 array.
2.5.15
VRH
The VRH pin is the positive reference voltage for the A/D converter.
2.5.16
VRL
The VRL pin is the negative reference voltage for the A/D converter.
2.5.17
PA0 - PA7/PB0 - PB7/PC0 - PC7
These 24 I/O lines comprise ports A, B and C. The state of any pin is software programmable, and all the pins are configured as inputs during power-on or reset. Under software control the PC2 pin can output the internal E-clock (see Section 4.2).
2.5.18
PD0/AN0-PD7/AN7
This 8-bit input only port (D) shares its pins with the A/D converter. When enabled, the A/D converter uses pins PD0/AN0 - PD7/AN7 as its analog inputs. On reset, the A/D converter is disabled which forces the port D pins to be input only port pins (see Section 8.5).
MC68HC05B6 Rev. 4.1
MODES OF OPERATION AND PIN DESCRIPTIONS
Freescale 2-13
2
THIS PAGE LEFT BLANK INTENTIONALLY
Freescale 2-14
MODES OF OPERATION AND PIN DESCRIPTIONS
MC68HC05B6 Rev. 4.1
3
MEMORY AND REGISTERS
The MC68HC05B6 MCU is capable of addressing 8192 bytes of memory and registers with its program counter. The memory map includes 5950 bytes of User ROM (including User vectors), 432 bytes of self check ROM, 176 bytes of RAM and 256 bytes of EEPROM.
3
3.1
Registers
All the I/O, control and status registers of the MC68HC05B6 are contained within the first 32-byte block of the memory map, as shown in Figure 3-1. The miscellaneous register is shown in Section 3.8 as this register contains bits which are relevant to several modules.
3.2
RAM
The user RAM comprises 176 bytes of memory, from $0050 to $00FF. This is shared with a 64 byte stack area. The stack begins at $00FF and may extend down to $00C0. Note: Using the stack area for data storage or temporary work locations requires care to prevent the data from being overwritten due to stacking from an interrupt or subroutine call.
3.3
ROM
The User ROM consists of 5950 bytes of ROM mapped as follows: * * * 48 bytes of page zero ROM from $0020 to $004F 5888 bytes of User ROM from $0800 to $1EFF 14 bytes of User vectors from $1FF2 to $1FFF
MC68HC05B6 Rev. 4.1
MEMORY AND REGISTERS
Freescale 3-1
3.4
Self-check ROM
There are two areas of self-check ROM (ROMI and ROMII) located from $0200 to $02BF (192 bytes) and $1F00 to $1FEF (240 bytes) respectively.
3
$0000 $0020
MC68HC05B6 I/O (32 bytes) Page 0 User ROM (48 bytes)
Registers
Port A data register Port B data register Port C data register Port D input data register Port A data direction register Port B data direction register Port C data direction register EEPROM/ECLK control register $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F
$0050 RAM (176 bytes) Stack OPTR (1 byte) Non protected (31 bytes) EEPROM (256 bytes) Protected (224 bytes) $0200 Self-check ROM I (192 bytes)
A/D data register A/D status/control register Pulse length modulation A Pulse length modulation B Miscellaneous register SCI baud rate register SCI control register 1 SCI control register 2 SCI status register SCI data register Timer control register Timer status register Capture high register 1 Capture low register 1 Compare high register 1
$00C0 $0100 $0101 $0120
$02C0 $0800 User ROM (5888 bytes) Self-check ROM II (240 bytes)
Compare low register 1 Counter high register Counter low register Alternate counter high register Alternate counter low register Capture high register 2 Capture low register 2 Compare high register 2 Compare low register 2
$1F00
$1FF0 SCI $1FF2-3 Timer overflow $1FF4-5 $1FF6-7 Timer output compare 1& 2 $1FF8-9 Timer input capture 1 & 2 External IRQ $1FFA-B $1FFC-D SWI $1FFE-F Reset/power-on reset
User vectors (14 bytes)
Options register $0100
Reserved
Figure 3-1 Memory map of the MC68HC05B6
Freescale 3-2
MEMORY AND REGISTERS
MC68HC05B6 Rev. 4.1
3.5
EEPROM
The user EEPROM consists of 256 bytes of memory located from address $0100 to $01FF. 255 bytes are general purpose and 1 byte is used by the option register. The non-volatile EEPROM is byte erasable. An internal charge pump provides the EEPROM voltage (VPP1), which removes the need to supply a high voltage for erase and programming functions. The charge pump is a capacitor/diode ladder network which will give a very high impedance output of around 20-30 M. The voltage of the charge pump is visible at the VPP1 pin. During normal operation of the device, where programming/erasing of the EEPROM array will occur, VPP1 should never be connected to either VDD or VSS as this could prevent the charge pump reaching the necessary programming voltage. Where it is considered dangerous to leave VPP1 unconnected for reasons of excessive noise in a system, it may be tied to VDD; this will protect the EEPROM data but will also increase power consumption, and therefore it is recommended that the protect bit function is used for regular protection of EEPROM data (see Section 3.5.5). In order to achieve a higher degree of security for stored data, there is no capability for bulk or row erase operations. The EEPROM control register ($0007) provides control of the EEPROM programming and erase operations. Warning: The VPP1 pin should never be connected to VSS, as this could cause permanent damage to the device.
3
3.5.1
EEPROM control register
Address bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 bit 2 bit 1 bit 0 State on reset
EEPROM/ECLK control
$0007
ECLK E1ERA E1LAT E1PGM 0000 0000
ECLK See Section 4.3 for a description of this bit. E1ERA -- EEPROM erase/programming bit Providing the E1LAT and E1PGM bits are at logic one, this bit indicates whether the access to the EEPROM is for erasing or programming purposes. 1 (set) - An erase operation will take place. A programming operation will take place.
0 (clear) -
Once the program/erase EEPROM address has been selected, E1ERA cannot be changed.
MC68HC05B6 Rev. 4.1
MEMORY AND REGISTERS
Freescale 3-3
E1LAT -- EEPROM programming latch enable bit 1 (set) - Address and data can be latched into the EEPROM for further program or erase operations, providing the E1PGM bit is cleared. Data can be read from the EEPROM. The E1ERA bit and the E1PGM bit are reset to zero when E1LAT is `0'.
3
0 (clear) -
STOP, power-on and external reset clear the E1LAT bit. Note: After the tERA1 erase time or tPROG1 programming time, the E1LAT bit has to be reset to zero in order to clear the E1ERA bit and the E1PGM bit.
E1PGM -- EEPROM charge pump enable/disable 1 (set) - Internal charge pump generator switched on. Internal charge pump generator switched off.
0 (clear) -
When the charge pump generator is on, the resulting high voltage is applied to the EEPROM array. This bit cannot be set before the data is selected, and once this bit has been set it can only be cleared by clearing the E1LAT bit. A summary of the effects of setting/clearing bits 0, 1 and 2 of the control register are give in Table 3-1.
Table 3-1 EEPROM control bits description
E1ERA 0 0 0 1 1 E1LAT E1PGM 0 1 1 1 1 0 0 1 0 1 Read condition Ready to load address/data for program/erase Byte programming in progress Ready for byte erase (load address) Byte erase in progress Description
Note:
All combinations are not shown in the above table, since the E1PGM and E1ERA bits are cleared when the E1LAT bit is at zero, and will result in a read condition.
Freescale 3-4
MEMORY AND REGISTERS
MC68HC05B6 Rev. 4.1
3.5.2
EEPROM read operation
To be able to read from EEPROM, the E1LAT bit has to be at logic zero, as shown in Table 3-1. While this bit is at logic zero, the E1PGM bit and the E1ERA bit are permanently reset to zero and the 256 bytes of EEPROM may be read as if it were a normal ROM area. The internal charge pump generator is automatically switched off since the E1PGM bit is reset. If a read operation is executed while the E1LAT bit is set (erase or programming sequence), data resulting from the operation will be $FF. Note: When not performing any programming or erase operation, it is recommended that EEPROM should remain in the read mode (E1LAT = 0)
3
3.5.3
EEPROM erase operation
To erase the contents of a byte of the EEPROM, the following steps should be taken: 1 Set the E1LAT bit.
1) Set the E1ERA bit (1& 2 may be done simultaneously with the same instruction). 2) Write address/data to the EEPROM address to be erased. 3) Set the E1PGM bit. 4) Wait for a time tERA1. 5) Reset the E1LAT bit (to logic zero). While an erase operation is being performed, any access of the EEPROM array will not be successful. The erased state of the EEPROM is $FF and the programmed state is $00. Note: Data written to the address to be erased is not used, therefore its value is not significant.
If a second word is to be erased, it is important that the E1LAT bit be reset before restarting the erasing sequence otherwise any write to a new address will have no effect. This condition provides a higher degree of security for the stored data. User programs must be running from the RAM or ROM as the EEPROM will have its address and data buses latched.
MC68HC05B6 Rev. 4.1
MEMORY AND REGISTERS
Freescale 3-5
3.5.4
EEPROM programming operation
To program a byte of EEPROM, the following steps should be taken: 1 Set the E1LAT bit. Write address/data to the EEPROM address to be programmed. Set the E1PGM bit. Wait for time tPROG1. Reset the E1LAT bit (to logic zero).
3
2 3 4 5
While a programming operation is being performed, any access of the EEPROM array will not be successful. Warning: To program a byte correctly, it has to have been previously erased. It is advised that this is done only for 01 transitions, as this saves excessive overwriting of EEPROM. If a second word is to be programmed, it is important that the E1LAT bit be reset before restarting the programming sequence otherwise any write to a new address will have no effect. This condition provides a higher degree of security for the stored data. User programs must be running from the RAM or ROM as the EEPROM will have its address and data buses latched. Note: 224 bytes of EEPROM (address $0120 to $01FF) can be program and erase protected under the control of bit 1 of the OPTR register detailed in Section 3.5.5.
3.5.5
Options register (OPTR)
This register (OPTR), located at $0100, contains the secure and protect functions for the EEPROM and allows the user to select options in a non-volatile manner. The contents of the OPTR register are loaded into data latches with each power-on or external reset.
Address Options (OPTR)(1) $0100 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 EE1P bit 0 State on reset
SEC Not affected
(1) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.
Freescale 3-6
MEMORY AND REGISTERS
MC68HC05B6 Rev. 4.1
EE1P - EEPROM protect bit In order to achieve a higher degree of protection, the EEPROM is effectively split into two parts, both working from the VPP1 charge pump. Part 1 of the EEPROM array (32 bytes from $0100 to $011F) cannot be protected; part 2 (224 bytes from $0120 to $01FF) is protected by the EE1P bit of the options register. 1 (set) - Part 2 of the EEPROM array is not protected; all 256 bytes of EEPROM can be accessed for any read, erase or programming operations Part 2 of the EEPROM array is protected; any attempt to erase or program a location will be unsuccessful
3
0 (clear) -
When this bit is set to 1 (erased), the protection will remain until the next power-on or external reset. EE1P can only be written to `0' when the ELAT bit in the EEPROM control register is set. SEC - Security bit This high security bit allows the user to secure the EEPROM data from external accesses. When the SEC bit is at `0', the EEPROM contents are secured by preventing any entry to test mode. The only way to erase the SEC bit to `1' externally is to enter self-check mode, at which time the entire EEPROM contents will be erased. When the SEC bit is changed, its new value will have no effect until the next external or power-on reset.
3.6
EEPROM during STOP mode
When entering STOP mode, the EEPROM is automatically set to the read mode and the VPP1 high voltage charge pump generator is automatically disabled.
3.7
EEPROM during WAIT mode
The EEPROM is not affected by WAIT mode. Any program/erase operation will continue as in normal operating mode. The charge pump is not affected by WAIT mode, therefore it is possible to wait the tERA1 erase time or tPROG1 programming time in WAIT mode. Under normal operating conditions, the charge pump generator is driven by the internal CPU clocks. When the operating frequency is low, e.g. during WAIT mode, the clocking should be done by the internal A/D RC oscillator. The RC oscillator is enabled by setting the ADRC bit of the A/D status/control register at $0009.
MC68HC05B6 Rev. 4.1
MEMORY AND REGISTERS
Freescale 3-7
Table 3-2 Register outline
State on reset Undefined Undefined PC2/ ECLK PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undefined Undefined 0000 0000 0000 0000 0000 0000 0 0 0 0 0 ECLK E1ERA E1LAT E1PGM 0000 0000 0000 0000 COCO ADRC ADON CH3 CH2 CH1 CH0 0000 0000 0000 0000 0000 0000 INTN SCT1 RIE RDRF INTE SCT0 M ILIE IDLE SFA SCT0 TE OR SFB SCR2 RE NF SM SCR1 RWU FE WDOG(2) ?001 000? SCR0 00uu uuuu LBCL SBK Undefined 0000 0000 1100 000u 0000 0000 ICIE ICF1 OCIE OCF1 TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0 TOF ICF2 OCF2 Undefined Undefined Undefined Undefined Undefined 1111 1111 1111 1100 1111 1111 1111 1100 Undefined Undefined Undefined Undefined EE1P SEC Not affected SPC1 R8 TIE TDRE SPC0 T8 TCIE TC
Register name
Address bit 7 $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
3
Port A data (PORTA) Port B data (PORTB) Port C data (PORTC) Port D data (PORTD) Port A data direction (DDRA) Port B data direction (DDRB) Port C data direction (DDRC) EEPROM/ECLK control A/D data (ADDATA) A/D status/control (ADSTAT) Pulse length modulation A (PLMA) Pulse length modulation B (PLMB) Miscellaneous SCI baud rate (BAUD) SCI control 1 (SCCR1) SCI control 2 (SCCR2) SCI status (SCSR) SCI data (SCDR) Timer control (TCR) Timer status (TSR) Input capture high 1 Input capture low 1 Output compare high 1 Output compare low 1 Timer counter high Timer counter low Alternate counter high Alternate counter low Input capture high 2 Input capture low 2 Output compare high 2 Output compare low 2 Options (OPTR)(3)
$000C POR(1) INTP $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F $0100
WAKE CPOL CPHA
(1) The POR bit is set each time there is a power-on reset. (2) The state of the WDOG bit after reset is dependent on the mask option selected; 1=watchdog enabled, 0=watchdog disabled. (3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.
Freescale 3-8
MEMORY AND REGISTERS
MC68HC05B6 Rev. 4.1
3.8
Miscellaneous register
Address Miscellaneous bit 7 bit 6 bit 5 INTN bit 4 INTE bit 3 SFA bit 2 SFB bit 1 SM bit 0 State on reset
$000C POR(1) INTP
WDOG(2) ?001 000?
(1) The POR bit is set each time there is a power-on reset. (2) The state of the WDOG bit after reset is dependent on the mask option selected; 1=watchdog enabled, 0=watchdog disabled.
3
POR -- Power-on reset bit (see Section 9.1) This bit is set each time the device is powered on. Therefore, the state of the POR bit allows the user to make a software distinction between a power-on and an external reset. This bit cannot be set by software and is cleared by writing it to zero. 1 (set) - A power-on reset has occurred. No power-on reset has occurred.
0 (clear) -
INTP, INTN -- External interrupt sensitivity options (see Section 9.2) These two bits allow the user to select which edge the IRQ pin will be sensitive to (see Table 3-3). Both bits can be written to only while the I-bit is set, and are cleared by power-on or external reset, thus the device is initialised with negative edge and low level sensitivity.
Table 3-3 IRQ sensitivity
INTP 0 0 1 1 INTN 0 1 0 1 IRQ sensitivity Negative edge and low level sensitive Negative edge only Positive edge only Positive and negative edge sensitive
INTE -- External interrupt enable (see Section 9.2) 1 (set) - External interrupt function (IRQ) enabled. External interrupt function (IRQ) disabled.
0 (clear) -
The INTE bit can be written to only while the I-bit is set, and is set by power-on or external reset, thus enabling the external interrupt function.
MC68HC05B6 Rev. 4.1
MEMORY AND REGISTERS
Freescale 3-9
SFA -- Slow or fast mode selection for PLMA (see Section 7.1) This bit allows the user to select the slow or fast mode of the PLMA pulse length modulation output.
3
1 (set)
-
Slow mode PLMA (4096 x timer clock period). Fast mode PLMA (256 x timer clock period).
0 (clear) -
SFB -- Slow or fast mode selection for PLMB (see Section 7.1) This bit allows the user to select the slow or fast mode of the PLMB pulse length modulation output. 1 (set) - Slow mode PLMB (4096 x timer clock period). Fast mode PLMB (256 x timer clock period).
0 (clear) - Note:
The highest speed of the PLM system corresponds to the frequency of the TOF bit being set, multiplied by 256. The lowest speed of the PLM system corresponds to the frequency of the TOF bit being set, multiplied by 16.
Warning: Because the SFA bit and SFB bit are not double buffered, it is mandatory to set the SFA bit and SFB bit to the desired values before writing to the PLM registers; not doing so could temporarily give incorrect values at the PLM outputs. SM -- Slow mode (see Section 2.4.3) 1 (set) - The system runs at a bus speed 16 times lower than normal (fOSC/32). SLOW mode affects all sections of the device, including SCI, A/D and timer. The system runs at normal bus speed (fOSC/2).
0 (clear) -
The SM bit is cleared by external or power-on reset. The SM bit is automatically cleared when entering STOP mode. WDOG -- Watchdog enable/disable (see Section 9.1.4) The WDOG bit can be used to enable the watchdog timer previously disabled by a mask option. Following a watchdog reset the state of the WDOG bit is as defined by the mask option specified. Once the watchdog is enabled, the WDOG bit acts as a reset mechanism for the watchdog counter. Writing a'1' to this bit clears the counter to its initial value and prevents a watchdog timeout. 1 (set) - Watchdog counter cleared and enabled. The watchdog cannot be disabled by software; writing a zero to this bit has no effect.
0 (clear) -
Freescale 3-10
MEMORY AND REGISTERS
MC68HC05B6 Rev. 4.1
4
INPUT/OUTPUT PORTS
In single-chip mode, the MC68HC05B6 has a total of 24 I/O lines, arranged as three 8-bit ports (A, B and C), and eight input-only lines, arranged as one 8-bit port (D). Each I/O line is individually programmable as either input or output, under the software control of the data direction registers. The 8-bit input-only port (D) shares its pins with the A/D converter, when the A/D converter is enabled. To avoid glitches on the output pins, data should be written to the I/O port data register before writing ones to the corresponding data direction register bits to set the pins to output mode.
4
4.1
Input/output programming
The bidirectional port lines may be programmed as inputs or outputs under software control. The direction of each pin is determined by the state of the corresponding bit in the port data direction register (DDR). Each port has an associated DDR. Any I/O port pin is configured as an output if its corresponding DDR bit is set to a logic one. A pin is configured as an input if its corresponding DDR bit is cleared to a logic zero. At power-on or reset, all DDRs are cleared, thus configuring all port pins as inputs. The data direction registers can be written to or read by the MCU. During the programmed output state, a read of the data register actually reads the value of the output data latch and not the I/O pin. The operation of the standard port hardware is shown schematically in Figure 4-1.
MC68HC05B6 Rev. 4.1
INPUT/OUTPUT PORTS
Freescale 4-1
M68HC05 internal connections
Data direction register bit
DDRn
Latched data register bit
DATA
Output buffer
I/O Pin
4
O/P data buffer Output Input buffer Input
DDRn

DATA 0 1 0 1
I/O Pin 0 1 tristate tristate
1 1 0 0
Figure 4-1 Standard I/O port structure
Table 4-1 shows the effect of reading from or writing to an I/O pin in various circumstances. Note that the read/write signal shown is internal and not available to the user.
Table 4-1 I/O pin states R/W 0 0 1 1 DDRn 0 1 0 1 Action of MCU write to/read of data bit The I/O pin is in input mode. Data is written into the output data latch. Data is written into the output data latch, and output to the I/O pin. The state of the I/O pin is read. The I/O pin is in output mode. The output data latch is read.
4.2
Ports A and B
These ports are standard M68HC05 bidirectional I/O ports, each comprising a data register and a data direction register. Reset does not affect the state of the data register, but clears the data direction register, thereby returning all port pins to input mode. Writing a `1' to any DDR bit sets the corresponding port pin to output mode.
Freescale 4-2
INPUT/OUTPUT PORTS
MC68HC05B6 Rev. 4.1
4.3
Port C
In addition to the standard port functions described for port A and B, port C pin 2 can be configured, using the ECLK bit of the EEPROM/ECLK control register, to output the CPU clock. If this is selected the corresponding DDR bit is automatically set and bit 2 of port C will always read the output data latch. The other port C pins are not affected by this feature.
Address EEPROM/ECLK control $0007 bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 bit 2 bit 1 bit 0 State on reset
ECLK E1ERA E1LAT E1PGM 0000 0000
4
ECLK -- External clock output bit 1 (set) - ECLK CPU clock is output on PC2. ECLK CPU clock is not output on PC2; port C acts as a normal I/O port.
0 (clear) -
The ECLK bit is cleared by power-on or external reset. It is not affected by the execution of a STOP or WAIT instruction. The timing diagram of the clock output is shown in Figure 4-2.
Internal clock (PHI2)
External clock (ECLK/PC2)
Output port (if write to output port)
Figure 4-2 ECLK timing diagram
4.4
Port D
This 8-bit input-only port shares its pins with the A/D converter subsystem. When the A/D converter is enabled, pins PD0-PD7 read the eight analog inputs to the A/D converter. Port D can be read at any time, however, if it is read during an A/D conversion sequence noise, may be injected on the analog inputs, resulting in reduced accuracy of the A/D. Furthermore, performing
MC68HC05B6 Rev. 4.1
INPUT/OUTPUT PORTS
Freescale 4-3
a digital read of port D with levels other than VDD or VSS on the port D pins will result in greater power dissipation during the read cycle. As port D is an input-only port there is no DDR associated with it. Also, at power up or external reset, the A/D converter is disabled, thus the port is configured as a standard input-only port. Note: It is recommended that all unused input ports and I/O ports be tied to an appropriate logic level (i.e. either VDD or VSS).
4
4.5 Port registers
The following sections explain in detail the individual bits in the data and control registers associated with the ports.
4.5.1
Port data registers A and B (PORTA and PORTB)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Undefined Undefined
Port A data (PORTA) Port B data (PORTB)
$0000 $0001
Each bit can be configured as input or output via the corresponding data direction bit in the port data direction register (DDRx). The state of the port data registers following reset is not defined.
4.5.2
Port data register C (PORTC)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 PC2/ ECLK bit 1 bit 0 State on reset Undefined
Port C data (PORTC)
$0002
Each bit can be configured as input or output via the corresponding data direction bit in the port data direction register (DDRx). In addition, bit 2 of port C is used to output the CPU clock if the ECLK bit in the EEPROM CTL/ECLK register is set (see Section 4.3). The state of the port data registers following reset is not defined.
Freescale 4-4
INPUT/OUTPUT PORTS
MC68HC05B6 Rev. 4.1
4.5.3
Port data register D (PORTD)
Address bit 7 PD7 bit 6 PD6 bit 5 PD5 bit 4 PD4 bit 3 PD3 bit 2 PD2 bit 1 PD1 bit 0 PD0 State on reset Undefined
Port D data (PORTD)
$0003
All the port D bits are input-only and are shared with the A/D converter. The function of each bit is determined by the ADON bit in the A/D status/control register. The state of the port data registers following reset is not defined.
4
bit 2 CH2 bit 1 CH1 bit 0 CH0 State on reset 0000 0000
4.5.3.1
A/D status/control register
Address bit 7 bit 6 bit 5 bit 4 0 bit 3 CH3
A/D status/control
$0009
COCO ADRC ADON
ADON -- A/D converter on 1 (set) - A/D converter is switched on; all port D pins act as analog inputs for the A/D converter. A/D converter is switched off; all port D pins act as input only pins.
0 (clear) -
Reset clears the ADON bit, thus configuring port D as an input only port.
4.5.4
Data direction registers (DDRA, DDRB and DDRC)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset 0000 0000 0000 0000 0000 0000
Port A data direction (DDRA) Port B data direction (DDRB) Port C data direction (DDRC)
$0004 $0005 $0006
Writing a `1' to any bit configures the corresponding port pin as an output; conversely, writing any bit to `0' configures the corresponding port pin as an input. Reset clears these registers, thus configuring all ports as inputs.
MC68HC05B6 Rev. 4.1
INPUT/OUTPUT PORTS
Freescale 4-5
4.6
Other port considerations
All output ports can emulate `open-drain' outputs. This is achieved by writing a zero to the relevant output port latch. By toggling the corresponding data direction bit, the port pin will either be an output zero or tri-state (an input). This is shown diagrammatically in Figure 4-3. When using a port pin as an `open-drain' output, certain precautions must be taken in the user software. If a read-modify-write instruction is used on a port where the `open-drain' is assigned and the pin at this time is programmed as an input, it will read it as a `one'. The read-modify-write instruction will then write this `one' into the output data latch on the next cycle. This would cause the `open-drain' pin not to output a `zero' when desired. Note: `Open-drain' outputs should not be pulled above VDD.
4
Read buffer output
(a)
A Data direction register bit DDRn Y
DDRn 1 1 0 0
A 0 1 0 1 0 1 0 1
Y
Normal operation - tri state tri state tri state
0 1 low -- high high
(b)
1 1 0 0 VDD VDD Px0 `Open-drain' output
`Open-drain'
(c)
DDRx, bit 0 = 0 Portx, bit 0 = 0 DDRx, bit 0 = 0 Portx, bit 0 = 0
Figure 4-3 Port logic levels
Freescale 4-6
INPUT/OUTPUT PORTS
MC68HC05B6 Rev. 4.1
5
PROGRAMMABLE TIMER
The programmable timer on the MC68HC05B6 consists of a 16-bit read-only free-running counter, with a fixed divide-by-four prescaler, plus the input capture/output compare circuitry. The timer can be used for many purposes including measuring pulse length of two input signals and generating two output signals. Pulse lengths for both input and output signals can vary from several microseconds to many seconds. In addition, it works in conjunction with the pulse length modulation (PLM) system, which can also be referred to as the pulse width modulation system, to execute two 8-bit D/A PLM (pulse length modulation) conversions, with a choice of two repetition rates. The timer is also capable of generating periodic interrupts or indicating passage of an arbitrary multiple of four CPU cycles. A block diagram is shown in Figure 5-1, and timing diagrams are shown in Figure 5-2, Figure 5-3, Figure 5-4 and Figure 5-5. The timer has a 16-bit architecture, hence each specific functional segment is represented by two 8-bit registers (except the PLMA and PLMB which use one 8-bit register for each). These registers contain the high and low byte of that functional segment. Accessing the low byte of a specific timer function allows full control of that function; however, an access of the high byte inhibits that specific timer function until the low byte is also accessed. The 16-bit programmable timer is monitored and controlled by a group of sixteen registers, full details of which are contained in this section. Note: A problem may arise if an interrupt occurs in the time between the high and low bytes being accessed. To prevent this, the I-bit in the condition code register (CCR) should be set while manipulating both the high and low byte register of a specific timer function, ensuring that an interrupt does not occur.
5
5.1
Counter
The key element in the programmable timer is a 16-bit, free-running counter or counter register, preceded by a prescaler that divides the internal processor clock by four. The prescaler gives the timer a resolution of 2s if the internal bus clock is 2 MHz. The counter is incremented during the low portion of the internal bus clock. Software can read the counter at any time without affecting its value.
MC68HC05B6 Rev. 4.1
PROGRAMMABLE TIMER
Freescale 5-1
Internal bus 8 Internal processor clock High byte Output compare register 1 Low byte $0016 $0017 High byte Output compare register 2 Low byte $001E $001F High byte 8-bit buffer Low byte High byte Low byte High byte Low byte
/4
16-bit $0018 free-running $0019 counter Counter alternate register $001A $001B
Input capture $0014 register 1 $0015
Input capture $001C register 2 $001D
5
COP watchdog counter input To PLM Internal timer bus
Output compare circuit 1
Output compare circuit 2
Overflow detect circuit
Edge detect circuit 1
Edge detect circuit 2
TCAP2 pin
TCAP1 pin
D
Q Latch
TCMP2 pin
+
C
D 7
ICF1
Q Latch
TCMP1 pin
6
OCF1
5
TOF
4
ICF2
3
OCF2
Timer status register $0013
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1
+
OLVL1
C
Timer control register $0012
Interrupt circuit Input capture interrupt $1FF8,9 Output compare interrupt $1FF6,7 Overflow interrupt $1FF4,5
Figure 5-1 16-bit programmable timer block diagram
Freescale 5-2
PROGRAMMABLE TIMER
MC68HC05B6 Rev. 4.1
5.1.1
Counter register and alternate counter register
Address Timer counter high Timer counter low $0018 $0019 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset 1111 1111 1111 1100 State on reset 1111 1111 1111 1100
Address Alternate counter high Alternate counter low $001A $001B
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
The double-byte, free-running counter can be read from either of two locations, $18-$19 (counter register) or $1A-$1B (alternate counter register). A read from only the less significant byte (LSB) of the free-running counter ($19 or $1B) receives the count value at the time of the read. If a read of the free-running counter or alternate counter register first addresses the more significant byte (MSB) ($18 or $1A), the LSB is transferred to a buffer. This buffer value remains fixed after the first MSB read, even if the user reads the MSB several times. This buffer is accessed when reading the free-running counter or alternate counter register LSB and thus completes a read sequence of the total counter value. In reading either the free-running counter or alternate counter register, if the MSB is read, the LSB must also be read to complete the sequence. If the timer overflow flag (TOF) is set when the counter register LSB is read then a read of the timer status register (TSR) will clear the flag. The alternate counter register differs from the counter register only in that a read of the LSB does not clear TOF. Therefore, where it is critical to avoid the possibility of missing timer overflow interrupts due to clearing of TOF, the alternate counter register should be used. The free-running counter is set to $FFFC during power-on and external reset and is always a read-only register. During a power-on reset, the counter begins running after the oscillator start-up delay. Because the free-running counter is 16 bits preceded by a fixed divide-by-4 prescaler, the value in the free-running counter repeats every 262,144 internal bus clock cycles. TOF is set when the counter overflows (from $FFFF to $0000); this will cause an interrupt if TOIE is set. In some particular timing control applications it may be desirable to reset the 16-bit free running counter under software control. When the low byte of the counter ($19 or $1B) is written to, the counter is configured to its reset value ($FFFC). The divide-by-4 prescaler is also reset and the counter resumes normal counting operation. All of the flags and enable bits remain unaltered by this operation. If access has previously been made to the high byte of the free-running counter ($18 or $1A), then the reset counter operation terminates the access sequence. Warning: This operation may affect the function of the watchdog system (see Section 9.1.4). The PLM results will also be affected while resetting the counter.
5
MC68HC05B6 Rev. 4.1
PROGRAMMABLE TIMER
Freescale 5-3
5.2
Timer control and status
The various functions of the timer are monitored and controlled using the timer control and status registers described below.
5.2.1
Timer control register (TCR)
The timer control register ($0012) is used to enable the input captures (ICIE), output compares (OCIE), and timer overflow (TOIE) functions as well as forcing output compares (FOLV1 and FOLV2), selecting input edge sensitivity (IEDG1) and levels of output polarity (OLV1 and OLV2).
5
Timer control (TCR)
Address $0012
bit 7 ICIE
bit 6 OCIE
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State on reset
TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0
ICIE -- Input captures interrupt enable If this bit is set, a timer interrupt is enabled whenever the ICF1 or ICF2 status flag (in the timer status register) is set. 1 (set) - Interrupt enabled. Interrupt disabled.
0 (clear) -
OCIE -- Output compares interrupt enable If this bit is set, a timer interrupt is enabled whenever the OCF1 or OCF2 status flag (in the timer status register) is set. 1 (set) - Interrupt enabled. Interrupt disabled.
0 (clear) -
TOIE -- Timer overflow interrupt enable If this bit is set, a timer interrupt is enabled whenever the TOF status flag (in the timer status register) is set. 1 (set) - Interrupt enabled. Interrupt disabled.
0 (clear) -
Freescale 5-4
PROGRAMMABLE TIMER
MC68HC05B6 Rev. 4.1
FOLV2 -- Force output compare 2 This bit always reads as zero, hence writing a zero to this bit has no effect. Writing a one at this position will force the OLV2 bit to the corresponding output level latch, thus appearing at the TCMP2 pin. Note that this bit does not affect the OCF2 bit of the status register (see Section 5.4.3). 1 (set) - OLV2 bit forced to output level latch. No effect.
0 (clear) -
FOLV1 -- Force output compare 1 This bit always reads as zero, hence writing a zero to this bit has no effect. Writing a one at this position will force the OLV1 bit to the corresponding output level latch, thus appearing at the TCMP1 pin. Note that this bit does not affect the OCF1 bit of the status register (see Section 5.4.3). 1 (set) - OLV1 bit forced to output level latch. No effect.
5
0 (clear) -
OLV2 -- Output level 2 When OLV2 is set a high output level will be clocked into the output level register by the next successful output compare, and will appear on the TCMP2 pin. When clear, it will be a low level which will appear on the TCMP2 pin. 1 (set) - A high output level will appear on the TCMP2 pin. A low output level will appear on the TCMP2 pin.
0 (clear) -
IEDG1 -- Input edge 1 When IEDG1 is set, a positive-going edge on the TCAP1 pin will trigger a transfer of the free-running counter value to the input capture register 1. When clear, a negative-going edge triggers the transfer. 1 (set) - TCAP1 is positive-going edge sensitive. TCAP1 is negative-going edge sensitive.
0 (clear) - Note:
There is no need for an equivalent bit for the input capture register 2 as TCAP2 is negative-going edge sensitive only.
OLV1 -- Output level 1 When OLV1 is set a high output level will be clocked into the output level register by the next successful output compare, and will appear on the TCMP1 pin. When clear, it will be a low level which will appear on the TCMP1 pin. 1 (set) - A high output level will appear on the TCMP1 pin. A low output level will appear on the TCMP1 pin.
0 (clear) -
MC68HC05B6 Rev. 4.1
PROGRAMMABLE TIMER
Freescale 5-5
5.2.2
Timer status register (TSR)
The timer status register ($13) is a read only register and contains the status bits corresponding to the four timer interrupt conditions - ICF1,OCF1, TOF, ICF2 and OCF2. Accessing the timer status register satisfies the first condition required to clear the status bits. The remaining step is to access the register corresponding to the status bit.
Address Timer status (TSR) $0013 bit 7 ICF1 bit 6 OCF1 bit 5 TOF bit 4 ICF2 bit 3 OCF2 bit 2 bit 1 bit 0 State on reset Undefined
5
ICF1 -- Input capture flag 1 This bit is set when the selected polarity of edge is detected by the input capture edge detector 1 at TCAP1; an input capture interrupt will be generated, if ICIE is set. ICF1 is cleared by reading the TSR and then the input capture low register 1 ($15). 1 (set) - A valid input capture has occurred. No input capture has occurred.
0 (clear) -
OCF1 -- Output compare flag 1 This bit is set when the output compare 1 register contents match those of the free-running counter; an output compare interrupt will be generated if OCIE is set. OCF1 is cleared by reading the TSR and then reading or writing the output compare 1 low register ($17). 1 (set) - A valid output compare has occurred. No output compare has occurred.
0 (clear) -
TOF -- Timer overflow status flag This bit is set when the free-running counter overflows from $FFFF to $0000; a timer overflow interrupt will occur if TOIE is set. TOF is cleared by reading the TSR and the counter low register ($19). 1 (set) - Timer overflow has occurred. No timer overflow has occurred.
0 (clear) -
When using the timer overflow function and reading the free-running counter at random times to measure an elapsed time, a problem may occur whereby the timer overflow flag is unintentionally cleared if: 1 The timer status register is read or written when TOF is set, and
1) The LSB of the free-running counter is read, but not for the purpose of servicing the flag. Reading the alternate counter register instead of the counter register will avoid this potential problem.
Freescale 5-6
PROGRAMMABLE TIMER
MC68HC05B6 Rev. 4.1
ICF2 -- Input capture flag 2 This bit is set when a negative edge is detected by the input capture edge detector 2 at TCAP2; an input capture interrupt will be generated if ICIE is set. ICF2 is cleared by reading the TSR and then the input capture low register 2 ($1D). 1 (set) - A valid (negative) input capture has occurred. No input capture has occurred.
0 (clear) -
OCF2 -- Output compare flag 2 This bit is set when the output compare 2 register contents match those of the free-running counter; an output compare interrupt will be generated if OCIE is set. OCF2 is cleared by reading the TSR and then reading or writing the output compare 2 low register ($1F). 1 (set) - A valid output compare has occurred. No output compare has occurred.
5
0 (clear) -
5.3
Input capture
`Input capture' is a technique whereby an external signal is used to trigger a read of the free running counter. In this way it is possible to relate the timing of an external signal to the internal counter value, and hence to elapsed time. There are two input capture registers: input capture register 1 (ICR1) and input capture register 2 (ICR2). The same input capture interrupt enable bit (ICIE) is used for the two input captures.
5.3.1
Input capture register 1 (ICR1)
Address Input capture high 1 Input capture low 1 $0014 $0015 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Undefined Undefined
The two 8-bit registers that make up the 16-bit input capture register 1 are read-only, and are used to latch the value of the free-running counter after the input capture edge detector circuit 1 senses a valid transition at TCAP1. The level transition that triggers the counter transfer is defined by the input edge bit (IEDG1). When an input capture 1 occurs, the corresponding flag ICF1 in TSR is set. An interrupt can also accompany an input capture 1 provided the ICIE bit in TCR is set. The 8 most significant bits are stored in the input capture high 1 register at $14, the 8 least significant bits in the input capture low 1 register at $15.
MC68HC05B6 Rev. 4.1
PROGRAMMABLE TIMER
Freescale 5-7
5
The result obtained from an input capture will be one greater than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. This delay is required for internal synchronization. Resolution is one count of the free-running counter, which is four internal bus clock cycles. The free-running counter contents are transferred to the input capture register 1 on each valid signal transition whether the input capture 1 flag (ICF1) is set or clear. The input capture register 1 always contains the free-running counter value that corresponds to the most recent input capture 1. After a read of the input capture 1 register MSB ($14), the counter transfer is inhibited until the LSB ($15) is also read. This characteristic causes the time used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. A read of the input capture 1 register LSB ($15) does not inhibit the free-running counter transfer since the two actions occur on opposite edges of the internal bus clock. Reset does not affect the contents of the input capture 1 register, except when exiting STOP mode (see Section 5.6).
5.3.2
Input capture register 2 (ICR2)
Address Input capture high 2 Input capture low 2 $001C $001D bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Undefined Undefined
The two 8-bit registers that make up the 16-bit input capture register 2 are read-only, and are used to latch the value of the free-running counter after the input capture edge detector circuit 2 senses a negative transition at pin TCAP2. When an input capture 2 occurs, the corresponding flag ICF2 in TSR is set. An interrupt can also accompany an input capture 2 provided the ICIE bit in TCR is set.The 8 most significant bits are stored in the input capture 2 high register at $1C, the 8 least significant bits in the input capture 2 low register at $1D. The result obtained from an input capture will be one greater than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. This delay is required for internal synchronization. Resolution is one count of the free-running counter, which is four internal bus clock cycles. The free-running counter contents are transferred to the input capture register 2 on each negative signal transition whether the input capture 2 flag (IC2F) is set or clear. The input capture register 2 always contains the free-running counter value that corresponds to the most recent input capture 2. After a read of the input capture register 2 MSB ($1C), the counter transfer is inhibited until the LSB ($1D) is also read. This characteristic causes the time used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. A read of the input capture register 2 LSB ($1C) does not inhibit the free-running counter transfer since the two actions occur on opposite edges of the internal bus clock. Reset does not affect the contents of the input capture 2 register, except when exiting STOP mode (see Section 5.6).
Freescale 5-8
PROGRAMMABLE TIMER
MC68HC05B6 Rev. 4.1
5.4
Output compare
`Output compare' is a technique which may be used, for example, to generate an output waveform, or to signal when a specific time period has elapsed, by presetting the output compare register to the appropriate value. There are two output compare registers: output compare register 1 (OCR1) and output compare register 2 (OCR2), both of which are read or write registers. Note: The same output compare interrupt enable bit (OCIE) is used for the two output compares.
5.4.1
Output compare register 1 (OCR1)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Undefined Undefined
5
Output compare high 1 Output compare low 1
$0016 $0017
The 16-bit output compare register 1 is made up of two 8-bit registers at locations $16 (MSB) and $17 (LSB). The contents of the output compare register 1 are compared with the contents of the free-running counter continually and, if a match is found, the corresponding output compare flag (OCF1) in the timer status register is set and the output level (OLVL1) is transferred to pin TCMP1. The output compare register 1 values and the output level bit should be changed after each successful comparison to establish a new elapsed timeout. An interrupt can also accompany a successful output compare provided the corresponding interrupt enable bit (OCIE) is set. (The free-running counter is updated every four internal bus clock cycles.) After a processor write cycle to the output compare register 1 containing the MSB ($16), the output compare function is inhibited until the LSB ($17) is also written. The user must write both bytes (locations) if the MSB is written first. A write made only to the LSB ($17) will not inhibit the compare 1 function. The processor can write to either byte of the output compare register 1 without affecting the other byte. The output level (OLVL1) bit is clocked to the output level register and hence to the TCMP1 pin whether the output compare flag 1 (OCF1) is set or clear. The minimum time required to update the output compare register 1 is a function of the program rather than the internal hardware. Because the output compare flag 1 and the output compare register 1 are not defined at power on, and not affected by reset, care must be taken when initializing output compare functions with software. The following procedure is recommended: - - - Write to output compare high 1 to inhibit further compares; Read the timer status register to clear OCF1 (if set); Write to output compare low 1 to enable the output compare 1 function.
MC68HC05B6 Rev. 4.1
PROGRAMMABLE TIMER
Freescale 5-9
The purpose of this procedure is to prevent the OCF1 bit from being set between the time it is read and the write to the corresponding output compare register. All bits of the output compare register are readable and writable and are not altered by the timer hardware or reset. If the compare function is not needed, the two bytes of the output compare register can be used as storage locations.
5.4.2
Output compare register 2 (OCR2)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Undefined Undefined
5
Output compare high 2 Output compare low 2
$001E $001F
The 16-bit output compare register 2 is made up of two 8-bit registers at locations $1E (MSB) and $1F (LSB). The contents of the output compare register 2 are compared with the contents of the free-running counter continually and, if a match is found, the corresponding output compare flag (OCF2) in the timer status register is set and the output level (OLVL2) is transferred to pin TCMP2. The output compare register 2 values and the output level bit should be changed after each successful comparison to establish a new elapsed timeout. An interrupt can also accompany a successful output compare provided the corresponding interrupt enable bit (OCIE) is set. (The free-running counter is updated every four internal bus clock cycles.) After a processor write cycle to the output compare register 2 containing the MSB ($1E), the output compare function is inhibited until the LSB ($1F) is also written. The user must write both bytes (locations) if the MSB is written first. A write made only to the LSB ($1F) will not inhibit the compare 2 function. The processor can write to either byte of the output compare register 2 without affecting the other byte. The output level (OLVL2) bit is clocked to the output level register and hence to the TCMP2 pin whether the output compare flag 2 (OCF2) is set or clear. The minimum time required to update the output compare register 2 is a function of the program rather than the internal hardware. Because the output compare flag 2 and the output compare register 2 are not defined at power on, and not affected by reset, care must be taken when initializing output compare functions with software. The following procedure is recommended: - - - Write to output compare high 2 to inhibit further compares; Read the timer status register to clear OCF2 (if set); Write to output compare low 2 to enable the output compare 2 function.
Freescale 5-10
PROGRAMMABLE TIMER
MC68HC05B6 Rev. 4.1
The purpose of this procedure is to prevent the OCF1 bit from being set between the time it is read and the write to the corresponding output compare register. All bits of the output compare register are readable and writable and are not altered by the timer hardware or reset. If the compare function is not needed, the two bytes of the output compare register can be used as storage locations.
5.4.3
Software force compare
A software force compare is required in many applications. To achieve this, bit 3 (FOLV1 for OCR1) and bit 4 (FOLV2 for OCR2) in the timer control register are used. These bits always read as `zero', but a write to `one' causes the respective OLVL1 or OLVL2 values to be copied to the respective output level (TCMP1 and TCMP2 pins). Internal logic is arranged such that in a single instruction, one can change OLVL1 and/or OLVL2, at the same time causing a forced output compare with the new values of OLVL1 and OLVL2. In conjunction with normal compare, this function allows a wide range of applications including fixed frequency generation. Note: A software force compare will affect the corresponding output pin TCMP1 and/or TCMP2, but will not affect the compare flag, thus it will not generate an interrupt.
5
5.5
Pulse Length Modulation (PLM)
The programmable timer works in conjunction with the PLM system to execute two 8-bit D/A PLM conversions, with a choice of two repetition rates (see Section 7).
5.5.1
Pulse length modulation registers A and B (PLMA/PLMB)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset 0000 0000 State on reset 0000 0000
Pulse length modulation A (PLMA)
$000A
Address Pulse length modulation B (PLMB) $000B
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
MC68HC05B6 Rev. 4.1
PROGRAMMABLE TIMER
Freescale 5-11
5.6
Timer during STOP mode
When the MCU enters STOP mode, the timer counter stops counting and remains at that particular count value until STOP mode is exited by an interrupt. If STOP mode is exited by power-on or external reset, the counter is forced to $FFFC but if it is exited by external interrupt (IRQ) then the counter resumes from its stopped value. Another feature of the programmable timer is that if at least one valid input capture edge occurs at one of the TCAP pins while in STOP mode, the corresponding input capture detect circuitry is armed. This action does not wake the MCU or set any timer flags, but when the MCU does wake-up there will be an active input capture flag (and data) from that first valid edge which occurred during STOP mode.
5
If STOP mode is exited by an external reset then no such input capture flag or data action takes place even if there was a valid input capture edge (at one of the TCAP pins) during STOP mode.
5.7
Timer during WAIT mode
The timer system is not affected by WAIT mode and continues normal operation. Any valid timer interrupt will wake-up the system.
5.8
Timer state diagrams
The relationships between the internal clock signals, the counter contents and the status of the flag bits are shown in the following figures. It should be noted that the signals labelled `internal' (processor clock, timer clocks and reset) are not available to the user.
Freescale 5-12
PROGRAMMABLE TIMER
MC68HC05B6 Rev. 4.1
Internal processor clock Internal reset
Internal timer clocks
T00 T01 T10 T11
$FFFC $FFFD $FFFE $FFFF
16-bit counter External reset or end of POR Note:
5
Figure 5-2 Timer state timing diagram for reset
The counter and timer control registers are the only ones affected by power-on or external reset.
Internal processor clock
Internal timer clocks
T00 T01 T10 T11
$F123 $F124 $F125 $F126
16-bit counter Input edge Internal capture latch Input capture register Input capture flag
}
$????
}
}
} $F124
Note:
If the input edge occurs in the shaded area from one timer state T10 to the next timer state T10, then the input capture flag will be set during the next T11 state.
Figure 5-3 Timer state timing diagram for input capture
MC68HC05B6 Rev. 4.1
PROGRAMMABLE TIMER
Freescale 5-13
Internal processor clock
Internal timer clocks
T00 T01 T10 T11
$F456
(Note 1)
16-bit counter Output compare register Compare register latch Output compare flag and TCMP1,2 Note: 1 1)
$F457
$F458 $F457
$F459
5
CPU writes $F457
(Note 1)
(Note 2)
The CPU write to the compare registers may take place at any time, but a compare only occurs at timer state T01. Thus a four cycle difference may exist between the write to the compare register and the actual compare. The output compare flag is set at the timer state T11 that follows the comparison match ($F457 in this example).
Figure 5-4 Timer state timing diagram for output compare
Internal processor clock
Internal timer clocks
T00 T01 T10 T11
$FFFF $0000 $0001 $0002
16-bit counter Timer overflow flag Note:
The timer overflow flag is set at timer state T11 (transition of counter from $FFFF to $0000). It is cleared by a read of the timer status register during the internal processor clock high time, followed by a read of the counter low register.
Figure 5-5 Timer state timing diagram for timer overflow
Freescale 5-14
PROGRAMMABLE TIMER
MC68HC05B6 Rev. 4.1
6
SERIAL COMMUNICATIONS INTERFACE
A full-duplex asynchronous serial communications interface (SCI) is provided with a standard non-return-to-zero (NRZ) format and a variety of baud rates. The SCI transmitter and receiver are functionally independent and have their own baud rate generator; however they share a common baud rate prescaler and data format. The serial data format is standard mark/space (NRZ) and provides one start bit, eight or nine data bits, and one stop bit. The SCLK pin is the output of the transmitter clock. It outputs the transmitter data clock for synchronous transmission (no clocks on start bit and stop bit, and a software option to send clock on last data bit). This allows control of peripherals containing shift registers (e.g. LCD drivers). Phase and polarity of these clocks are software programmable. Any SCI bidirectional communication requires a two-wire system: receive data in (RDI) and transmit data out (TDO). `Baud' and `bit rate' are used synonymously in the following description.
6
6.1
* * * * * * * * * *
SCI two-wire system features
Standard NRZ (mark/space) format Advanced error detection method with noise detection for noise duration of up to 1/16th bit time Full-duplex operation (simultaneous transmit and receive) 32 software selectable baud rates Different baud rates for transmit and receive; for each transmit baud rate, 8 possible receive baud rates Software selectable word length (eight or nine bits) Separate transmitter and receiver enable bits Capable of being interrupt driven Transmitter clocks available without altering the regular transmitter or receiver functions Four separate enable bits for interrupt control
MC68HC05B6 Rev. 4.1
SERIAL COMMUNICATIONS INTERFACE
Freescale 6-1
Internal bus SCI interrupt +
$0011 (See note)
Transmit data register
$0011 (See note)
Receive data register
& TDO pin Transmit data shift register
&
&
&
+
$000F SCCR2 TIE TCIE RIE ILIE TE RE SBK RWU SCSR $0010
7 6 5 4 3 2 1 0
Receive data shift register
RDI pin
6
7 TRDE
6 TC
5 RDRF
4 IDLE
3 OR
2 NF
1 FE
Wake up unit
TE
SBK
7 Flag control Receiver control Receiver clock
Transmitter control Transmitter clock
SCLK pin
Clock extraction phase and polarity control
7 R8 6 T8 5 4 M 3 WAKE 2 CPOL 1 CPHA 0 LBCL SCCR1 $000E
Note:
The serial communications data register (SCI SCDR) is controlled by the internal R/W signal. It is the transmit data register when written to and the receive data register when read.
Figure 6-1 Serial communications interface block diagram
Freescale 6-2
SERIAL COMMUNICATIONS INTERFACE
MC68HC05B6 Rev. 4.1
6.2
* * * * * *
SCI receiver features
Receiver wake-up function (idle line or address bit) Idle line detection Framing error detection Noise detection Overrun detection Receiver data register full flag
6.3
* * *
SCI transmitter features
Transmit data register empty flag Transmit complete flag Send break
6
6.4
Functional description
A block diagram of the SCI is shown in Figure 6-1. Option bits in serial control register1 (SCCR1) select the `wake-up' method (WAKE bit) and data word length (M-bit) of the SCI. SCCR2 provides control bits that individually enable the transmitter and receiver, enable system interrupts and provide the wake-up enable bit (RWU) and the send break code bit (SBK). Control bits in the baud rate register (BAUD) allow the user to select one of 32 different baud rates for the transmitter and receiver (see Section 6.11.5). Data transmission is initiated by writing to the serial communications data register (SCDR). Provided the transmitter is enabled, data stored in the SCDR is transferred to the transmit data shift register. This transfer of data sets the transmit data register empty flag (TDRE) in the SCI status register (SCSR) and generates an interrupt (if transmitter interrupts are enabled). The transfer of data to the transmit data shift register is synchronized with the bit rate clock (see Figure 6-2). All data is transmitted least significant bit first. Upon completion of data transmission, the transmission complete flag (TC) in the SCSR is set (provided no pending data, preamble or break is to be sent) and an interrupt is generated (if the transmit complete interrupt is enabled). If the transmitter is disabled, and the data, preamble or break (in the transmit data shift register) has been sent, the TC bit will also be set. This will also generate an interrupt if the transmission complete interrupt enable bit (TCIE) is set. If the transmitter is disabled during a transmission, the character being transmitted will be completed before the transmitter gives up control of the TDO pin.
MC68HC05B6 Rev. 4.1
SERIAL COMMUNICATIONS INTERFACE
Freescale 6-3
When SCDR is read, it contains the last data byte received, provided that the receiver is enabled. The receive data register full flag bit (RDRF) in the SCSR is set to indicate that a data byte has been transferred from the input serial shift register to the SCDR; this will cause an interrupt if the receiver interrupt is enabled. The data transfer from the input serial shift register to the SCDR is synchronized by the receiver bit rate clock. The OR (overrun), NF (noise), or FE (framing) error flags in the SCSR may be set if data reception errors occurred. An idle line interrupt is generated if the idle line interrupt is enabled and the IDLE bit (which detects idle line transmission) in SCSR is set. This allows a receiver that is not in the wake-up mode to detect the end of a message or the preamble of a new message, or to resynchronize with the transmitter. A valid character must be received before the idle line condition or the IDLE bit will not be set and idle line interrupt will not be generated. The SCP0 and SCP1 bits function as a prescaler for SCR0-SCR2 to generate the receiver baud rate and for SCT0-SCT2 to generate the transmitter baud rate. Together, these eight bits provide multiple transmitter/receiver rate combinations for a given crystal frequency (see Figure 6-2). This register should only be written to while both the transmitter and receiver are disabled (TE=0, RE=0).
Internal processor clock SCP0 - SCP1 prescaler rate control (/ NP)
6
SCT0 - SCT2 transmitter rate control (/ NT)
SCR0 - SCR2 receiver rate control (/ NR)
/16
Transmitter clock Note:
SCP1
SPC0
SCT2
SCT1
SCT0
SCR2
SCR1
SCR0
$000D
7
6
5
4
3
2
1
0 Receiver clock
Baud rate register
There is a fixed rate divide-by-16 before the transmitter to compensate for the inherent divide-by-16 of the receiver (sampling). This means that by loading the same value for both the transmitter and receiver baud rate selector, the same baud rates can be obtained.
Figure 6-2 SCI rate generator division
Freescale 6-4
SERIAL COMMUNICATIONS INTERFACE
MC68HC05B6 Rev. 4.1
6.5
Data format
Receive data or transmit data is the serial data that is transferred to the internal data bus from the receive data input pin (RDI) or from the internal bus to the transmit data output pin (TDO). The non-return-to-zero (NRZ) data format shown in Figure 6-3 is used and must meet the following criteria: - - - - - The idle line is brought to a logic one state prior to transmission/reception of a character. A start bit (logic zero) is used to indicate the start of a frame. The data is transmitted and received least significant bit first. A stop bit (logic one) is used to indicate the end of a frame. A frame consists of a start bit, a character of eight or nine data bits, and a stop bit. A break is defined as the transmission or reception of a low (logic zero) for at least one complete frame time (10 zeros for 8-bit format, 11 zeros for 9-bit).
Control bit M selects 8 or 9 bit data
6

0 Stop Start
Idle line Start
0
1
2
3
4
5
6
7
8
Figure 6-3 Data format
6.6
Receiver wake-up operation
The receiver logic hardware also supports a receiver wake-up function which is intended for systems having more than one receiver. With this function a transmitting device directs messages to an individual receiver or group of receivers by passing addressing information as the initial byte(s) of each message. The wake-up function allows receivers not addressed to remain in a dormant state for the remainder of the unwanted message. This eliminates any further software overhead to service the remaining characters of the unwanted message and thus improves system performance. The receiver is placed in wake-up mode by setting the receiver wake-up bit (RWU) in the SCCR2 register. While RWU is set, all of the receiver related status flags (RDRF, IDLE, OR, NF, and FE) are inhibited (cannot become set). Note that the idle line detect function is inhibited while the RWU bit is set. Although RWU may be cleared by a software write to SCCR2, it would be unusual to do so. Normally RWU is set by software and is cleared automatically in hardware by one of the two methods described below.
MC68HC05B6 Rev. 4.1
SERIAL COMMUNICATIONS INTERFACE
Freescale 6-5
6.6.1
Idle line wake-up
In idle line wake-up mode, a dormant receiver wakes up as soon as the RDI line becomes idle. Idle is defined as a continuous logic high level on the RDI line for ten (or eleven) full bit times. Systems using this type of wake-up must provide at least one character time of idle between messages to wake up sleeping receivers, but must not allow any idle time between characters within a message.
6.6.2
Address mark wake-up
6
In address mark wake-up, the most significant bit (MSB) in a character is used to indicate whether it is an address (1) or data (0) character. Sleeping receivers will wake up whenever an address character is received. Systems using this method for wake-up would set the MSB of the first character of each message and leave it clear for all other characters in the message. Idle periods may be present within messages and no idle time is required between messages for this wake-up method.
6.7
Receive data in (RDI)
Receive data is the serial data that is applied through the input line and the SCI to the internal bus. The receiver circuitry clocks the input at a rate equal to 16 times the baud rate. This time is referred to as the RT rate in Figure 6-4 and as the receiver clock in Figure 6-2. The receiver clock generator is controlled by the baud rate register, as shown in Figure 6-1 and Figure 6-2; however, the SCI is synchronized by the start bit, independent of the transmitter. Once a valid start bit is detected, the start bit, each data bit and the stop bit are sampled three times at RT intervals 8 RT, 9 RT and 10 RT (1 RT is the position where the bit is expected to start), as shown in Figure 6-5. The value of the bit is determined by voting logic which takes the value of the majority of the samples. A noise flag is set when all three samples on a valid start bit or data bit or the stop bit do not agree.
6.8
Start bit detection
When the input (idle) line is detected low, it is tested for three more sample times (referred to as the start edge verification samples in Figure 6-4). If at least two of these three verification samples detect a logic zero, a valid start bit has been detected, otherwise the line is assumed to be idle. A noise flag is set if one of the three verification samples detect a logic one, thus a valid start bit could be assumed with a set noise flag present.
Freescale 6-6
SERIAL COMMUNICATIONS INTERFACE
MC68HC05B6 Rev. 4.1
16X internal sampling clock
RT clock edges for all three examples Idle RDI 1 1 1 1 1 1 1 1 1 1 1 Start qualifiers
1RT 2RT 3RT 4RT 5RT 6RT 7RT 8RT
Start 0 0 0 0 Start edge verification samples Noise 0 1 0
Start RDI 1 1 1 1 1 1 1 1 1 1 1 0
Noise RDI 1 1 1 1 1 0 1 1 1 1 1
Start 0 0 0 0
6
Figure 6-4 SCI examples of start bit sampling technique
Previous bit RDI
16RT 1RT
Present bit
Samples
Next bit
< < <
8RT 9RT 10RT
16RT 1RT
Figure 6-5 SCI sampling technique used on all bits
If there has been a framing error without detection of a break (10 zeros for 8 bit format or 11 zeros for 9 bit format), the circuit continues to operate as if there actually was a stop bit, and the start edge will be placed artificially. The last bit received in the data shift register is inverted to a logic one, and the three logic one start qualifiers (shown in Figure 6-4) are forced into the sample shift register during the interval when detection of a start bit is anticipated (see Figure 6-6); therefore, the start bit will be accepted no sooner than it is anticipated.
MC68HC05B6 Rev. 4.1
SERIAL COMMUNICATIONS INTERFACE
Freescale 6-7
If the receiver detects that a break (RDRF = 1, FE = 1, receiver data register = $0000) produced the framing error, the start bit will not be artificially induced and the receiver must actually detect a logic one before the start bit can be recognised (see Figure 6-7).
Data
Expected stop
Artificial edge Start bit
Data
RDI
Data samples a) Case 1: receive line low during artificial edge
Data
Expected stop
Start edge Start bit
Data
6
RDI
Data samples b) Case 2: receive line high during expected start edge
Figure 6-6 Artificial start following a framing error
Expected stop Break RDI
Detected as valid start edge Start bit

Data samples
Start qualifiers
Start edge verification samples
Figure 6-7 SCI start bit following a break
6.9
Transmit data out (TDO)
Transmit data is the serial data from the internal data bus that is applied through the SCI to the output line. Data format is as discussed in Section 6.5 and shown in Figure 6-3. The transmitter generates a bit time by using a derivative of the RT clock, thus producing a transmission rate equal to 1/16th that of the receiver sample clock (assuming the same baud rate is selected for both the receiver and transmitter).
Freescale 6-8
SERIAL COMMUNICATIONS INTERFACE
MC68HC05B6 Rev. 4.1
6.10
SCI synchronous transmission
The SCI transmitter allows the user to control a one way synchronous serial transmission. The SCLK pin is the clock output of the SCI transmitter. No clocks are sent to that pin during start bit and stop bit. Depending on the state of the LBCL bit (bit 0 of SCCR1), clocks will or will not be activated during the last valid data bit (address mark). The CPOL bit (bit 2 of SCCR1) allows the user to select the clock polarity, and the CPHA bit (bit 1 of SCCR1) allows the user to select the phase of the external clock (see Figure 6-8, Figure 6-9 and Figure 6-10). During idle, preamble and send break, the external SCLK clock is not activated. These options allow the user to serially control peripherals which consist of shift registers, without losing any functions of the SCI transmitter which can still talk to other SCI receivers. These options do not affect the SCI receiver which is independent of the transmitter. The SCLK pin works in conjunction with the TDO pin. When the SCI transmitter is disabled (TE = 0), the SCLK and TDO pins go to the high impedance state. Note: The LBCL, CPOL and CPHA bits have to be selected before enabling the transmitter to ensure that the clocks function correctly. These bits should not be changed while the transmitter is enabled.
6
RDI TDO SCLK
Data out Data in
Asynchronous (e.g. Modem)
MC68HC05B6
Data in Clock
Output port
Enable
Synchronous (e.g. shift register, display driver, etc.)
Figure 6-8 SCI example of synchronous and asynchronous transmission
MC68HC05B6 Rev. 4.1
SERIAL COMMUNICATIONS INTERFACE
Freescale 6-9
6.11
SCI registers
The SCI system is configured and controlled by five registers: SCDR, SCCR1, SCCR2, SCSR, and BAUD.
6.11.1
Serial communications data register (SCDR)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset 0000 0000
SCI data (SCDR)
$0011
6
The SCDR is controlled by the internal R/W signal and performs two functions in the SCI. It acts as the receive data register (RDR) when it is read and as the transmit data register (TDR) when it is written. Figure 6-1 shows this register as two separate registers, RDR and TDR. The RDR provides the interface from the receive shift register to the internal data bus and the TDR provides the parallel interface from the internal data bus to the transmit shift register. The receive data register is a read-only register containing the last byte of data received from the shift register for the internal data bus. The RDR full bit (RDRF) in the serial communications status register is set to indicate that a byte has been transferred from the input serial shift register to the SCDR. The transfer is synchronized with the receiver bit rate clock (from the receiver control) as shown in Figure 6-1. All data is received with the least significant bit first. The transmit data register (TDR) is a write-only register containing the next byte of data to be applied to the transmit shift register from the internal data bus. As long as the transmitter is enabled, data stored in the SCDR is transferred to the transmit shift register (after the current byte in the shift register has been transmitted). The transfer is synchronized with the transmitter bit rate clock (from the transmitter control) as shown in Figure 6-1. All data is received with the least significant bit first.
6.11.2
Serial communications control register 1 (SCCR1)
Address bit 7 R8 bit 6 T8 bit 5 bit 4 M bit 3 bit 2 bit 1 bit 0 LBCL State on reset Undefined
SCI control 1 (SCCR1)
$000E
WAKE CPOL CPHA
The SCI control register 1 (SCCR1) contains control bits related to the nine data bit character format, the receiver wake-up feature and the options to output the transmitter clocks for synchronous transmissions.
Freescale 6-10
SERIAL COMMUNICATIONS INTERFACE
MC68HC05B6 Rev. 4.1
R8 -- Receive data bit 8 This read-only bit is the ninth serial data bit received when the SCI system is configured for nine data bit operation (M = 1). The most significant bit (bit 8) of the received character is transferred into this bit at the same time as the remaining eight bits (bits 0-7) are transferred from the serial receive shifter to the SCI receive data register. T8 -- Transmit data bit 8 This read/write bit is the ninth data bit to be transmitted when the SCI system is configured for nine data bit operation (M = 1). When the eight low order bits (bits 0-7) of a transmit character are transferred from the SCI data register to the serial transmit shift register, this bit (bit 8) is transferred to the ninth bit position of the shifter. M -- Mode (select character format) The read/write M-bit controls the character length for both the transmitter and receiver at the same time. The 9th data bit is most commonly used as an extra stop bit or it can also be used as a parity bit (see Table 6-1). 1 (set) - Start bit, 9 data bits, 1 stop bit. Start bit, 8 data bits, 1 stop bit.
6
0 (clear) -
Table 6-1 Method of receiver wake-up
WAKE 0 1 1 x = Don't care M x 0 1 Method of receiver wake-up Detection of an idle line allows the next data type received to cause the receive data register to fill and produce an RDRF flag. Detection of a received one in the eighth data bit allows an RDRF flag and associated error flags. Detection of a received one in the ninth data bit allows an RDRF flag and associated error flags.
WAKE -- Wake-up mode select This bit allows the user to select the method for receiver wake-up. The WAKE bit can be read or written to any time. See Table 6-1. 1 (set) - Wake-up on address mark; if RWU is set, SCI will wake-up if the 8th (if M=0) or 9th (if M=1) bit received on the Rx line is set. Wake-up on idle line; if RWU is set, SCI will wake-up after 11 (if M=0) or 12 (if M=1) consecutive `1's on the Rx line.
0 (clear) -
MC68HC05B6 Rev. 4.1
SERIAL COMMUNICATIONS INTERFACE
Freescale 6-11
CPOL - Clock polarity This bit allows the user to select the polarity of the clocks to be sent to the SCLK pin. It works in conjunction with the CPHA bit to produce the desired clock-data relation (see Figure 6-9 and Figure 6-10). 1 (set) - Steady high value at SCLK pin outside transmission window. Steady low value at SCLK pin outside transmission window.
0 (clear) -
This bit should not be manipulated while the transmitter is enabled. CPHA - Clock phase This bit allows the user to select the phase of the clocks to be sent to the SCLK pin. This bit works in conjunction with the CPOL bit to produce the desired clock-data relation (see Figure 6-9 and Figure 6-10).
6
1 (set)
-
SCLK clock line activated at beginning of data bit. SCLK clock line activated in middle of data bit.
0 (clear) -
This bit should not be manipulated while the transmitter is enabled.
Idle or preceding transmission clock (CPOL = 0, CPHA = 0) clock (CPOL = 0, CPHA = 1) clock (CPOL = 1, CPHA = 0) clock (CPOL = 1, CPHA = 1) data
Start
M = 0 (8 data bits) * * * * 0 1 2 3 4 5 6 7
Stop
Idle or next transmission
Start LSB
MSB Stop * LBCL bit controls last data clock
Figure 6-9 SCI data clock timing diagram (M=0)
Freescale 6-12
SERIAL COMMUNICATIONS INTERFACE
MC68HC05B6 Rev. 4.1
Idle or preceding transmission clock (CPOL = 0, CPHA = 0) clock (CPOL = 0, CPHA = 1) clock (CPOL = 1, CPHA = 0) clock (CPOL = 1, CPHA = 1) data
Start
M = 1 (9 data bits) * * * * 0 1 2 3 4 5 6 7 8
Idle or next Stop transmission
Start LSB
MSB Stop * LBCL bit controls last data clock
6
Figure 6-10 SCI data clock timing diagram (M=1)
LBCL - Last bit clock This bit allows the user to select whether the clock associated with the last data bit transmitted (MSB) has to be output to the SCLK pin. The clock of the last data bit is output to the SCLK pin if the LBCL bit is a logic one, and is not output if it is a logic zero. The last bit is the 8th or 9th data bit transmitted depending on the 8 or 9 bit format selected by M-bit (seeTable 6-2). This bit should not be manipulated while the transmitter is enabled.
Table 6-2 SCI clock on SCLK pin
Number of clocks on SCLK pin 7 8 8 9
Data format 8 bit 8 bit 9 bit 9 bit
M-bit 0 0 1 1
LBCL bit 0 1 0 1
MC68HC05B6 Rev. 4.1
SERIAL COMMUNICATIONS INTERFACE
Freescale 6-13
6.11.3
Serial communications control register 2 (SCCR2)
The SCI control register 2 (SCCR2) provides the control bits that enable/disable individual SCI functions.
Address SCI control (SCCR2) $000F bit 7 TIE bit 6 TCIE bit 5 RIE bit 4 ILIE bit 3 TE bit 2 RE bit 1 RWU bit 0 SBK State on reset 0000 0000
TIE -- Transmit interrupt enable 1 (set) - TDRE interrupts enabled. TDRE interrupts disabled.
0 (clear) -
6
TCIE -- Transmit complete interrupt enable 1 (set) - TC interrupts enabled. TC interrupts disabled.
0 (clear) -
RIE -- Receiver interrupt enable 1 (set) - RDRF and OR interrupts enabled. RDRF and OR interrupts disabled.
0 (clear) -
ILIE -- Idle line interrupt enable 1 (set) - IDLE interrupts enabled. IDLE interrupts disabled.
0 (clear) -
TE -- Transmitter enable When the transmit enable bit is set, the transmit shift register output is applied to the TDO line and the corresponding clocks are applied to the SCLK pin. Depending on the state of control bit M (SCCR1), a preamble of 10 (M = 0) or 11 (M = 1) consecutive ones is transmitted when software sets the TE bit from a cleared state. If a transmission is in progress and a zero is written to TE, the transmitter will wait until after the present byte has been transmitted before placing the TDO and the SCLK pin in the idle, high impedance state. If the TE bit has been written to a zero and then set to a one before the current byte is transmitted, the transmitter will wait for that byte to be transmitted and will then initiate transmission of a new preamble. After this latest transmission, and provided the TDRE bit is set (no new data to transmit), the line remains idle (driven high while TE = 1); otherwise, normal transmission occurs. This function allows the user to neatly terminate a transmission sequence.
Freescale 6-14
SERIAL COMMUNICATIONS INTERFACE
MC68HC05B6 Rev. 4.1
After loading the last byte in the serial communications data register and receiving the TDRE flag, the user should clear TE. Transmission of the last byte will then be completed and the line will go idle. 1 (set) - Transmitter enabled. Transmitter disabled.
0 (clear) -
RE -- Receiver enable 1 (set) - Receiver enabled. Receiver disabled.
0 (clear) -
When RE is clear (receiver disabled) all the status bits associated with the receiver (RDRF, IDLE, OR, NF and FE) are inhibited. RWU -- Receiver wake-up When the receiver wake-up bit is set by the user software, it puts the receiver to sleep and enables the wake-up function. The type of wake-up mode for the receiver is determined by the WAKE bit discussed above (in the SCCR1). When the RWU bit is set, no status flags will be set. Flags which were set previously will not be cleared when RWU is set. If the WAKE bit is cleared, RWU is cleared by the SCI logic after receiving 10 (M = 0) or 11 (M =1) consecutive ones. Under these conditions, RWU cannot be set if the line is idle. If the WAKE bit is set, RWU is cleared after receiving an address bit. The RDRF flag will then be set and the address byte stored in the receiver data register. SBK -- Send break If the send break bit is toggled set and cleared, the transmitter sends 10 (M = 0) or 11 (M = 1) zeros and then reverts to idle sending data. If SBK remains set, the transmitter will continually send whole blocks of zeros (sets of 10 or 11) until cleared. At the completion of the break code, the transmitter sends at least one high bit to guarantee recognition of a valid start bit.
6
MC68HC05B6 Rev. 4.1
SERIAL COMMUNICATIONS INTERFACE
Freescale 6-15
6.11.4
Serial communications status register (SCSR)
Address bit 7 TDRE bit 6 TC bit 5 RDRF bit 4 IDLE bit 3 OR bit 2 NF bit 1 FE bit 0 State on reset 1100 000u
SCI status (SCSR)
$0010
The serial communications status register (SCSR) provides inputs to the interrupt logic circuits for generation of the SCI system interrupt. In addition, a noise flag bit and a framing error bit are also contained in the SCSR. TDRE -- Transmit data register empty flag This bit is set when the contents of the transmit data register are transferred to the serial shift register. New data will not be transmitted unless the SCSR register is read before writing to the transmit data register to clear the TDRE flag.
6
If the TDRE bit is clear, this indicates that the transfer has not yet occurred and a write to the serial communications data register will overwrite the previous value. The TDRE bit is cleared by accessing the serial communications status register (with TDRE set) followed by writing to the serial communications data register. TC -- Transmit complete flag This bit is set to indicate that the SCI transmitter has no meaningful information to transmit (no data in shifter, no preamble, no break). When TC is set the serial line will go idle (continuous MARK). The TC bit is cleared by accessing the serial communications status register (with TC set) followed by writing to the serial communications data register. It does not inhibit the transmitter function in any way. RDRF -- Receive data register full flag This bit is set when the contents of the receiver serial shift register are transferred to the receiver data register. If multiple errors are detected in any one received word, the NF and RDRF bits will be affected as appropriate during the same clock cycle. The RDRF bit is cleared when the serial communications status register is accessed (with RDRF set) followed by a read of the serial communications data register. IDLE -- Idle line detected flag This bit is set when a receiver idle line is detected (the receipt of a minimum of ten/eleven consecutive "1"s). This bit will not be set by the idle line condition when the RWU bit is set. This allows a receiver that is not in the wake-up mode to detect the end of a message, detect the preamble of a new message or resynchronize with the transmitter. The IDLE bit is cleared by accessing the serial communications status register (with IDLE set) followed by a read of the serial communications data register. Once cleared, IDLE will not be set again until after RDRF has been set, (i.e. until after the line has been active and becomes idle again).
Freescale 6-16
SERIAL COMMUNICATIONS INTERFACE
MC68HC05B6 Rev. 4.1
OR -- Overrun error flag This bit is set when a new byte is ready to be transferred from the receiver shift register to the receiver data register and the receive data register is already full (RDRF bit is set). Data transfer is inhibited until the RDRF bit is cleared. Data in the serial communications data register is valid in this case, but additional data received during an overrun condition (including the byte causing the overrun) will be lost. The OR bit is cleared when the serial communications status register is accessed (with OR set) followed by a read of the serial communications data register. NF -- Noise error flag This bit is set if there is noise on a `valid' start bit, any of the data bits or on the stop bit. The NF bit is not set by noise on the idle line nor by invalid start bits. If there is noise, the NF bit is not set until the RDRF flag is set. Each data bit is sampled three times as described in Section 6.7. The NF bit represents the status of the byte in the serial communications data register. For the byte being received (shifted in) there will be also a `working' noise flag, the value of which will be transferred to the NF bit when the serial data is loaded into the serial communications data register. The NF bit does not generate an interrupt because the RDRF bit gets set with NF and can be used to generate the interrupt. The NF bit is cleared when the serial communications status register is accessed (with NF set) followed by a read of the serial communications data register. FE -- Framing error flag This bit is set when the word boundaries in the bit stream are not synchronized with the receiver bit counter (generated by the reception of a logic zero bit where a stop bit was expected). The FE bit reflects the status of the byte in the receive data register and the transfer from the receive shifter to the receive data register is inhibited by an overrun. The FE bit is set during the same cycle as the RDRF bit but does not get set in the case of an overrun (OR). The framing error flag inhibits further transfer of data into the receive data register until it is cleared. The FE bit is cleared when the serial communications status register is accessed (with FE set) followed by a read of the serial communications data register.
6
MC68HC05B6 Rev. 4.1
SERIAL COMMUNICATIONS INTERFACE
Freescale 6-17
6.11.5
Baud rate register (BAUD)
The baud rate register provides the means to select two different or equivalent baud rates for the transmitter and receiver.
Address SCI baud rate (BAUD) $000D bit 7 SCP1 bit 6 SCP0 bit 5 SCT2 bit 4 SCT1 bit 3 SCT0 bit 2 SCR2 bit 1 SCR1 bit 0 State on reset
SCR0 00uu uuuu
SCP1, SCP0 -- Serial prescaler select bits These read/write bits determine the prescale factor, NP, by which the internal processor clock is divided before it is applied to the transmitter and receiver rate control dividers, NT and NR. This common prescaled output is used as the input to a divider that is controlled by the SCR0-SCR2 bits for the SCI receiver, and by the SCT0-SCT2 bits for the transmitter.
6
Table 6-3 First prescaler stage
SCP1 0 0 1 1 SCP0 0 1 0 1 Prescaler division ratio (NP) 1 3 4 13
SCT2, SCT1,SCT0 -- SCI rate select bits (transmitter) These three read/write bits select the baud rates for the transmitter. The prescaler output is divided by the factors shown in Table 6-4. Table 6-4 Second prescaler stage (transmitter)
SCT2 0 0 0 0 1 1 1 1 SCT1 0 0 1 1 0 0 1 1 SCT0 0 1 0 1 0 1 0 1 Transmitter division ratio (NT) 1 2 4 8 16 32 64 128
Freescale 6-18
SERIAL COMMUNICATIONS INTERFACE
MC68HC05B6 Rev. 4.1
SCR2, SCR1, SCR0 -- SCI rate select bits (receiver) These three read/write bits select the baud rates for the receiver. The prescaler output described above is divided by the factors shown in Table 6-5.
Table 6-5 Second prescaler stage (receiver)
SCR2 0 0 0 0 1 1 1 1 SCR1 0 0 1 1 0 0 1 1 SCR0 0 1 0 1 0 1 0 1 Receiver division ratio (NR) 1 2 4 8 16 32 64 128
6
The following equations are used to calculate the receiver and transmitter baud rates: f op baudTx = ---------------------------------16 * NP * NT f op baudRx = ----------------------------------16 * NP * NR where: NP = prescaler divide ratio NT = transmitter baud rate divide ratio NR = receiver baud rate divide ratio baudTx = transmitter baud rate baudRx = receiver baud rate fOSC = oscillator frequency
6.12
Baud rate selection
The flexibility of the baud rate generator allows many different baud rates to be selected. A particular baud rate may be generated in several ways by manipulating the various prescaler and division ratio bits. Table 6-6 shows the baud rates that can be achieved, for five typical crystal frequencies. These are effectively the highest baud rates which can be achieved using a given crystal.
MC68HC05B6 Rev. 4.1
SERIAL COMMUNICATIONS INTERFACE
Freescale 6-19
Table 6-6 SCI baud rate selection
Crystal frequency - fOSC (MHz) SCP1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SCP0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SCT/R2 SCT/R1 SCT/R0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 NP 1 1 1 1 1 1 1 1 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 13 13 13 13 13 13 13 13 NT/NR 1 2 4 8 16 32 64 128 1 2 4 8 16 32 64 128 1 2 4 8 16 32 64 128 1 2 4 8 16 32 64 128 4.194304 131072 65536 32768 16384 8192 4096 2048 1024 43691 21845 10923 5461 2731 1365 683 341 32768 16384 8192 4096 2048 1024 512 256 10082 5041 2521 1260 630 315 158 79 4.00 125000 62500 31250 15625 7813 3906 1953 977 41667 20833 10417 5208 2604 1302 651 326 31250 15625 7813 3906 1953 977 488 244 9615 4808 2404 1202 601 300 150 75 2.4576 76800 38400 19200 9600 4800 2400 1200 600 25600 12800 6400 3200 1600 800 400 200 19200 9600 4800 2400 1200 600 300 150 5908 2954 1477 738 369 185 92 46 2.00 62500 31250 15625 7813 3906 1953 977 488 20833 10417 5208 2604 1302 651 326 163 15625 7813 3906 1953 977 488 244 122 4808 2404 1202 601 300 150 75 38 1.8432 57600 28800 14400 7200 3600 1800 900 450 19200 9600 4800 2400 1200 600 300 150 14400 7200 3600 1800 900 450 225 113 4431 2215 1108 554 277 138 69 35
6
Note:
The examples shown above do not apply when the part is operating in slow mode (see Section 2.4.3).
Freescale 6-20
SERIAL COMMUNICATIONS INTERFACE
MC68HC05B6 Rev. 4.1
6.13
SCI during STOP mode
When the MCU enters STOP mode, the baud rate generator driving the receiver and transmitter is shut down. This stops all SCI activity. Both the receiver and the transmitter are unable to operate. If the STOP instruction is executed during a transmitter transfer, that transfer is halted. When STOP mode is exited as a result of an external interrupt, that particular transmission resumes. If the receiver is receiving data when the STOP instruction is executed, received data sampling is stopped (baud generator stops) and the rest of the data is lost. Warning: For the above reasons, all SCI transactions should be in the idle state when the STOP instruction is executed.
6.14
SCI during WAIT mode
6
The SCI system is not affected by WAIT mode and continues normal operation. Any valid SCI interrupt will wake-up the system. If required, the SCI system can be disabled prior to entering WAIT mode by writing a zero to the transmitter and receiver enable bits in the serial communication control register 2 at $000F. This action will result in a reduction of power consumption during WAIT mode.
MC68HC05B6 Rev. 4.1
SERIAL COMMUNICATIONS INTERFACE
Freescale 6-21
6
THIS PAGE LEFT BLANK INTENTIONALLY
Freescale 6-22
SERIAL COMMUNICATIONS INTERFACE
MC68HC05B6 Rev. 4.1
7
PULSE LENGTH D/A CONVERTERS
The pulse length D/A converter (PLM) system works in conjunction with the timer to execute two 8-bit D/A conversions, with a choice of two repetition rates. (See Figure 7-1.)
Data bus
8 PLMA register
8 PLMB register
7
`A' register buffer
`B' register buffer
`A' comparator
`B' comparator
PLMA D/A pin
R Latch S
R Latch S
PLMB D/A pin
Zero detector 8 SFA bit `A' multiplexer 16 8 `B' multiplexer 16
Zero detector
SFB bit
Timer bus
From timer
Figure 7-1 PLM system block diagram
MC68HC05B6 Rev. 4.1
PULSE LENGTH D/A CONVERTERS
Freescale 7-1
The D/A converter has two data registers associated with it, PLMA and PLMB.
Address Pulse length modulation A (PLMA) Pulse length modulation B (PLMB) $000A $000B bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset 0000 0000 0000 0000
This is a dual 8-bit resolution D/A converter associated with two output pins (PLMA and PLMB). The outputs are pulse length modulated signals whose duty cycle ratio may be modified. These signals can be used directly as PLMs, or the filtered average may be used as general purpose analog outputs. The longest repetition period is 4096 times the programmable timer clock period (CPU clock multiplied by four), and the shortest repetition period is 256 times the programmable timer clock period (the repetition rate frequencies for a 4 MHz crystal are 122 Hz and 1953 Hz respectively). Registers PLMA ($0A) and PLMB ($0B) are associated with the pulse length values of the two counters. A value of $00 loaded into these registers results in a continuously low output on the corresponding D/A output pin. A value of $80 results in a 50% duty cycle output, and so on, to the maximum value $FF corresponding to an output which is at `1' for 255/256 of the cycle. When the MCU makes a write to register PLMA or PLMB the new value will only be picked up by the D/A converters at the end of a complete cycle of conversion. This results in a monotonic change of the DC component at the output without overshoots or vicious starts (a vicious start is an output which gives totally erroneous PLM during the period immediately following an update of the PLM D/A registers). This feature is achieved by double buffering of the PLM D/A registers. Examples of PWM output waveforms are shown in Figure 7-2.
256 T
7
$00
$01 T
255 T
$80
128 T
128 T
$FF
255 T T = 4 CPU clocks in fast mode and 64 CPU clocks in slow mode
T
Figure 7-2 PLM output waveform examples
Freescale 7-2
PULSE LENGTH D/A CONVERTERS
MC68HC05B6 Rev. 4.1
Note:
Since the PLM system uses the timer counter, PLM results will be affected while resetting the timer counter. Both D/A registers are reset to $00 during power-on or external reset. WAIT mode does not affect the output waveform of the D/A converters.
7.1
Miscellaneous register
Address Miscellaneous $000C bit 7 POR bit 6 INTP bit 5 INTN bit 4 INTE bit 3 SFA bit 2 SFB bit 1 SM bit 0 State on reset
WDOG ?001 000?
SFA -- Slow or fast mode selection for PLMA This bit allows the user to select the slow or fast mode of the PLMA pulse length modulation output. 1 (set) - Slow mode PLMA (4096 x timer clock period). Fast mode PLMA (256 x timer clock period).
0 (clear) -
SFB -- Slow or fast mode selection for PLMB This bit allows the user to select the slow or fast mode of the PLMB pulse length modulation output. 1 (set) - Slow mode PLMB (4096 x timer clock period). Fast mode PLMB (256 x timer clock period).
7
0 (clear) -
The highest speed of the PLM system corresponds to the frequency of the TOF bit being set, multiplied by 256. The lowest speed of the PLM system corresponds to the frequency of the TOF bit being set, multiplied by 16. Because the SFA bit and SFB bit are not double buffered, it is mandatory to set them to the desired values before writing to the PLM registers; not doing so could temporarily give incorrect values at the PLM outputs. SM -- Slow mode 1 (set) - The system runs at a bus speed 16 times lower than normal (fOSC/32). SLOW mode affects all sections of the device, including SCI, A/D and timer. The system runs at normal bus speed (fOSC/2).
0 (clear) -
MC68HC05B6 Rev. 4.1
PULSE LENGTH D/A CONVERTERS
Freescale 7-3
The SM bit is cleared by external or power-on reset. The SM bit is automatically cleared when entering STOP mode. Note: The bits that are shown shaded in the above representation are explained individually in the relevant sections of this manual. The complete register plus an explanation of each bit can be found in Section 3.8
7.2
PLM clock selection
The slow/fast mode of the PLM D/A converters is selected by bits 1, 2, and 3 of the miscellaneous register at address $000C (SFA bit for PLMA and SFB bit for PLMB). The slow/fast mode has no effect on the D/A converters' 8-bit resolution (see Figure 7-3). Bus frequency (fOP) Timer clock
fOSC
/2
SM bit = 0
/4
x4096
SF bit = 1
7
PLM clock
/32
SM bit = 1
x256
SF bit = 0
Figure 7-3 PLM clock selection
7.3
PLM during STOP mode
On entering STOP mode, the PLM outputs remain at their particular level. When STOP mode is exited by an interrupt, the PLM systems resume regular operation. If STOP mode is exited by power-on or external reset the registers values are forced to $00.
7.4
PLM during WAIT mode
The PLM system is not affected by WAIT mode and continues normal operation.
Freescale 7-4
PULSE LENGTH D/A CONVERTERS
MC68HC05B6 Rev. 4.1
8
ANALOG TO DIGITAL CONVERTER
The analog to digital converter system consists of a single 8-bit successive approximation converter and a sixteen channel multiplexer. Eight of the channels are connected to the PD0/AN0 - PD7/AN7 pins of the MC68HC05B6 and the other eight channels are dedicated to internal reference points for test functions. The channel input pins do not have any internal output driver circuitry connected to them because such circuitry would load the analog input signals due to output buffer leakage current. There is one 8-bit result data register (address $08) and one 8-bit status/control register (address $09). The A/D converter is ratiometric and two dedicated pins, VRH and VRL, are used to supply the reference voltage levels for all analog inputs. These pins are used in preference to the system power supply lines because any voltage drops in the bonding wires of the heavily loaded supply pins could degrade the accuracy of the A/D conversion. An input voltage equal to or greater than VRH converts to $FF (full scale) with no overflow indication and an input voltage equal to VRL converts to $00. The A/D converter can operate from either the bus clock or an internal RC type oscillator. The internal RC type oscillator is activated by the ADRC bit in the A/D status/control register (ADSTAT) and can be used to give a sufficiently high clock rate to the A/D converter when the bus speed is too low to provide accurate results. When the A/D converter is not being used it can be disconnected, by clearing the ADON bit in the ADSTAT register, in order to save power (see Section 8.2.3). For further information on A/D converter operation please refer to the M68HC11 Reference Manual -- M68HC11RM/AD.
8
8.1
A/D converter operation
The A/D converter consists of an analog multiplexer, an 8-bit digital to analog converter capacitor array, a comparator and a successive approximation register (SAR) (see Figure 8-1). There are eleven options that can be selected by the multiplexer; AN0-AN7, VRH, (VRH+VRL)/2 or VRL. Selection is done via the CHx bits in the ADSTAT register (see Section 8.2.3). AN0-AN7 are the only input points for A/D conversion operations; the others are reference points that can be used for test purposes.
MC68HC05B6 Rev. 4.1
ANALOG TO DIGITAL CONVERTER
Freescale 8-1
The A/D reference input (AN0-AN7) is applied to a precision internal D/A converter. Control logic drives this D/A converter and the analog output is successively compared with the analog input sampled at the beginning of the conversion. The conversion is monotonic with no missing codes.
AN0 AN1 AN2
8-bit capacitive DAC with sample and hold
VRH VRL
AN4 AN5 AN6 AN7 VRH (VRH+VRL)/2 VRL
Analog MUX (Channel assignment)
AN3
Successive approximation register (SAR) and control
Result
A/D status/control register (ADSTAT)$09
CH0 CH1 CH2 CH3 0 ADON ADRC COCO
8
A/D result register (ADDATA) $08
Figure 8-1 A/D converter block diagram
The result of each successive comparison is stored in the SAR and, when the conversion is complete, the contents of the SAR are transferred to the read-only result data register ($08), and the conversion complete flag, COCO, is set in the A/D status/control register ($09). Warning: Any write to the A/D status/control register will abort the current conversion, reset the conversion complete flag and start a new conversion on the selected channel. At power-on or external reset, both the ADRC and ADON bits are cleared; thus the A/D is disabled.
Freescale 8-2
ANALOG TO DIGITAL CONVERTER
MC68HC05B6 Rev. 4.1
8.2 8.2.1
A/D registers Port D data register (PORTD)
Address Port D data (PORTD) $0003 bit 7 PD7 bit 6 PD6 bit 5 PD5 bit 4 PD4 bit 3 PD3 bit 2 PD2 bit 1 PD1 bit 0 PD0 State on reset Undefined
Port D is an input-only port which routes the eight analog inputs to the A/D converter. When the A/D converter is disabled, the pins are configured as standard input-only port pins, which can be read via the port D data register. Note: When the A/D function is enabled, pins PD0-PD7 will act as analog inputs. Using a pin or pins as A/D inputs does not affect the ability to read port D as static inputs; however, reading port D during an A/D conversion sequence may inject noise on the analog inputs and result in reduced accuracy of the A/D result. Performing a digital read of port D with levels other than VDD or VSS on the pins will result in greater power dissipation during the read cycle, and may give unpredictable results on the corresponding port D pins.
8.2.2
A/D result data register (ADDATA)
Address A/D data (ADDATA) $0008 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset 0000 0000
8
ADDATA is a read-only register which is used to store the results of A/D conversions. Each result is loaded into the register from the SAR and the conversion complete flag, COCO, in the ADSTAT register is set.
MC68HC05B6 Rev. 4.1
ANALOG TO DIGITAL CONVERTER
Freescale 8-3
8.2.3
A/D status/control register (ADSTAT)
Address bit 7 bit 6 bit 5 bit 4 0 bit 3 CH3 bit 2 CH2 bit 1 CH1 bit 0 CH0 State on reset 0000 0000
A/D status/control (ADSTAT)
$0009
COCO ADRC ADON
COCO -- Conversion complete flag 1 (set) - COCO is set each time a conversion is complete, allowing the new result to be read from the A/D result data register ($08). The converter then starts a new conversion. COCO is cleared by reading the result data register or writing to the status/control register.
0 (clear) -
Reset clears the COCO flag. ADRC -- A/D RC oscillator control The ADRC bit allows the user to control the A/D RC oscillator, which is used to provide a sufficiently high clock rate to the A/D to ensure accuracy when the chip is running at low speeds. 1 (set) - When the ADRC bit is set, the A/D RC oscillator is turned on and, if ADON is set, the A/D runs from the RC oscillator clock. See Table 8-1. When the ADRC bit is cleared, the A/D RC oscillator is turned-off and, if ADON is set, the A/D runs from the CPU clock.
8
Note:
0 (clear) -
When the A/D RC oscillator is turned on, it takes a time tADRC to stabilize (see Table 11-6 and Table 11-7). During this time A/D conversion results may be inaccurate. If the MCU bus clock falls below 1MHz, the A/D RC oscillator should be switched on.
Power-on or external reset clears the ADRC bit.
Table 8-1 A/D clock selection
RC A/D oscillator converter OFF OFF ON ON OFF ON OFF ON
ADRC 0 0 1 1
ADON 0 1 0 1
Comments A/D switched off. A/D using CPU clock. Allows the RC oscillator to stabilize. A/D using RC oscillator clock.
Freescale 8-4
ANALOG TO DIGITAL CONVERTER
MC68HC05B6 Rev. 4.1
ADON -- A/D converter on The ADON bit allows the user to enable/disable the A/D converter. 1 (set) - A/D converter is switched on. A/D converter is switched off.
0 (clear) -
When the A/D converter is switched on, it takes a time tADON for the current sources to stabilize (see Table 11-6 and Table 11-7). Using the A/D converter before this time has elapsed may result in the incorrect operation of the A/D, even after tADON has elapsed. In this case ADON would have to be cleared and set again. Power-on or external reset will clear the ADON bit, thus disabling the A/D converter. CH3-CH0 -- A/D channels 3, 2, 1 and 0 The CH3-CH0 bits allow the user to determine which channel of the A/D converter multiplexer is selected. See Table 8-2 for channel selection. Reset clears the CH0-CH3 bits.
Table 8-2 A/D channel assignment
CH3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CH2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CH1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CH0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Channel selected AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 VRH pin (high) (VRH + VRL) / 2 VRL pin (low) VRL pin (low) VRL pin (low) VRL pin (low) VRL pin (low) VRL pin (low)
8
MC68HC05B6 Rev. 4.1
ANALOG TO DIGITAL CONVERTER
Freescale 8-5
8.3
A/D converter during STOP mode
When the MCU enters STOP mode with the A/D converter turned on, the A/D clocks are stopped and the A/D converter is disabled for the duration of STOP mode, including the 4064 cycles start-up time. If the A/D RC oscillator is in operation it will also be disabled.
8.4
A/D converter during WAIT mode
The A/D converter is not affected by WAIT mode and continues normal operation. In order to reduce power consumption the A/D converter can be disconnected, under software control using the ADON bit and the ADRC bit in the A/D status/control register at $0009, before entering WAIT mode.
8.5
Port D analog input
8
The external analog voltage value to be processed by the A/D converter is sampled on an internal capacitor through a resistive path, provided by input-selection switches and a sampling aperture time switch, as shown in Figure 8-2. Sampling time is limited to 12 bus clock cycles. After sampling, the analog value is stored on the capacitor and held until the end of conversion. During this hold time, the analog input is disconnected from the internal A/D system and the external voltage source sees a high impedance input. The equivalent analog input during sampling is an RC low-pass filter with a minimum resistance of 50 k and a capacitance of at least 10pF. It should be noted that these are typical values measured at room temperature.
Input protection device Analog input pin < 2pF
50k
+ 20V - 0.7V 1 A junction leakage 10pF DAC capacitance VRL
Note:
The analog switch is closed during the 12 cycle sample time only.
Figure 8-2 Electrical model of an A/D input pin
Freescale 8-6
ANALOG TO DIGITAL CONVERTER
MC68HC05B6 Rev. 4.1
9
RESETS AND INTERRUPTS
9.1 Resets
The MC68HC05B6 can be reset in three ways: by the initial power-on reset function, by an active low input to the RESET pin or by a computer operating properly (COP) watchdog reset. Any of these resets will cause the program to go to its starting address, specified by the contents of memory locations $1FFE and $1FFF, and cause the interrupt mask bit in the condition code register to be set.
tVDDR VDD VDD threshold (1-2V typical) tOXOV
OSC1 Internal processor clock tPORL tCYC
9
tRL (or tDOGL) (External hardware reset)
RESET Internal address bus Internal data bus
(Internal power-on reset)
1FFE 1FFE 1FFE 1FFE 1FFF
New PC
1FFE 1FFE 1FFE 1FFE
1FFF
New PC Op code
Reset sequence
New PCH New PCL Op code
Reset sequence
New PCH New PCL
Program execution begins
Program execution begins
Figure 9-1 Reset timing diagram
MC68HC05B6 Rev. 4.1
RESETS AND INTERRUPTS
Freescale 9-1
9.1.1
Power-on reset
A power-on reset occurs when a positive transition is detected on VDD. The power-on reset function is strictly for power turn-on conditions and should not be used to detect drops in the power supply voltage. The power-on circuitry provides a stabilization delay (tPORL) from when the oscillator becomes active. If the external RESET pin is low at the end of this delay then the processor remains in the reset state until RESET goes high. The user must ensure that the voltage on VDD has risen to a point where the MCU can operate properly by the time tPORL has elapsed. If there is doubt, the external RESET pin should remain low until the voltage on VDD has reached the specified minimum operating voltage. This may be accomplished by connecting an external RC circuit to this pin to generate a power-on reset (POR). In this case, the time constant must be great enough to allow the oscillator circuit to stabilize. During power-on reset, the RESET pin is driven low during a tPORL delay start-up sequence. tPORL is defined by a user specified mask option to be either 16 cycles or 4064 cycles (see Section 1.2). A software distinction between a power-on reset and an external reset can be made using the POR bit in the miscellaneous register (see Section 9.1.2).
9.1.2
Miscellaneous register
Address Miscellaneous bit 7 bit 6 bit 5 INTN bit 4 INTE bit 3 SFA bit 2 SFB bit 1 SM bit 0 State on reset
$000C POR(1) INTP
WDOG(2) ?001 000?
9
(1) The POR bit is set each time there is a power-on reset. (2) The state of the WDOG bit after reset is dependent on the mask option selected; 1=watchdog enabled, 0=watchdog disabled.
POR -- Power-on reset bit This bit is set each time the device is powered on. Therefore, the state of the POR bit allows the user to make a software distinction between a power-on and an external reset. This bit cannot be set by software and is cleared by writing it to zero. 1 (set) - A power-on reset has occurred. No power-on reset has occurred.
0 (clear) - Note:
The bits shown shaded in the above representation are explained individually in the relevant sections of this manual. The complete register plus an explanation of each bit can be found in Section 3.8.
Freescale 9-2
RESETS AND INTERRUPTS
MC68HC05B6 Rev. 4.1
9.1.3
RESET pin
When the oscillator is running in a stable condition, the MCU is reset when a logic zero is applied to the RESET input for a minimum period of 1.5 machine cycles (tCYC). An internal Schmitt Trigger is used to improve noise immunity on this pin. When the RESET pin goes high, the MCU will resume operation on the following cycle. When a reset condition occurs internally, i.e. from POR or the COP watchdog, the RESET pin provides an active-low open drain output signal which may be used to reset external hardware. Current limitation to protect the pull-down device is provided in case an RC type external reset circuit is used.
9.1.4
Computer operating properly (COP) watchdog reset
The watchdog counter system consists of a divide-by-8 counter, preceded by a fixed divide-by-4 and a fixed divide-by-256 prescaler, plus control logic as shown in Figure 9-2. The divide-by-8 counter can be reset by software.
Main CPU clock
S R Latch
Power-on
fOSC/2 /4 fOSC/32 prescaler
/ 256 (Bit 7 of free running counter)
/ 8 watchdog counter Enable Reset
Reset pin
+
9
Schmitt trigger Input protection
WDOG bit
Control logic
Figure 9-2 Watchdog system block diagram
Warning: The input to the watchdog system is derived from the carry output of bit 7 of the free running timer counter. Therefore, a reset of the timer may affect the period of the watchdog timeout. The watchdog system can be automatically enabled, following power-on or external reset, via a mask option (see Section 1.2), or it can be enabled by software by writing a `1' to the WDOG bit in the miscellaneous register at $000C (see Section 9.1.2). Once enabled, the watchdog system
MC68HC05B6 Rev. 4.1
RESETS AND INTERRUPTS
Freescale 9-3
cannot be disabled by software (writing a `zero' to the WDOG bit has no effect at any time). In addition, the WDOG bit acts as a reset mechanism for the watchdog counter. Writing a `1' to this bit clears the counter to its initial value and prevents a watchdog timeout. WDOG -- Watchdog enable/disable The WDOG bit can be used to enable the watchdog timer previously disabled by a mask option. Following a watchdog reset the state of the WDOG bit is as defined by the mask option specified. 1 (set) - Watchdog enabled and counter cleared. The watchdog cannot be disabled by software; writing a zero to this bit has no effect.
0 (clear) -
The divide-by-8 watchdog counter will generate a main reset of the chip when it reaches its final state; seven clocks are necessary to bring the watchdog counter from its clear state to its final state. This reset appears after time tDOG since the last clear or since the enable of the watchdog counter system. The watchdog counter, therefore, has to be cleared periodically, by software, with a period less than tDOG. The reset generated by the watchdog system is apparent at the RESET pin (see Figure 9-2). The RESET pin level is re-entered in the control logic, and when it has been maintained at level `zero' for a minimum of tDOGL, the RESET pin is released.
9.1.4.1
COP watchdog during STOP mode
9
The STOP instruction is inhibited when the watchdog system is enabled. If a STOP instruction is executed while the watchdog system is enabled, then a watchdog reset will occur as if there were a watchdog timeout. In the case of a watchdog reset due to a STOP instruction, the oscillator will not be affected, thus there will be no tPORL cycles start-up delay. On start-up, the watchdog will be configured according to the user specified mask option.
9.1.4.2
COP watchdog during WAIT mode
The state of the watchdog during WAIT mode is selected via a mask option (see Section 1.2) to be one of the options below: Watchdog enabled -- the watchdog counter will continue to operate during WAIT mode and a reset will occur after time tDOG. Watchdog disabled -- on entering WAIT mode, the watchdog counter system is reset and disabled. On exiting WAIT mode the counter resumes normal operation.
Freescale 9-4
RESETS AND INTERRUPTS
MC68HC05B6 Rev. 4.1
9.1.5
Functions affected by reset
When processing stops within the MCU for any reason, i.e. power-on reset, external reset or the execution of a STOP or WAIT instruction, various internal functions of the MCU are affected. Table 9-1 shows the resulting action of any type of system reset, but not necessarily in the order in which they occur.
Table 9-1 Effect of RESET, POR, STOP and WAIT
Function/effect Timer prescaler set to zero Timer counter set to $FFFC All timer enable bits cleared (disable) Data direction registers cleared (inputs) Stack pointer set to $00FF Force internal address bus to restart Vector $1FFE, $1FFF Interrupt mask bit (I-bit CCR) set to 1 Interrupt mask bit (I-bit CCR) cleared Set interrupt enable bit (INTE) Set POR bit in miscellaneous register Reset STOP latch Reset IRQ latch Reset WAIT latch SCI disabled SCI status bits cleared (except TDRE and TC) SCI interrupt enable bits cleared SCI status bits TDRE and TC set Oscillator disabled for 4064 cycles Timer clock cleared SCI clock cleared A/D disabled SM bit in the miscellaneous register cleared Watchdog counter reset WDOG bit in the miscellaneous register reset EEPROM control bits (see Section 3.5.1) RESET x x x x x x x x - x - x x x x x x x - - - x x x x x POR x x x x x x x x - x x x x x x x x x x x x x x x x x WAIT - - - - - - - - x - - - - - - - - - - - - - - x - - STOP - - - - - - - - x - - - - - - - - - x x x x x x x x
9
x = Described action takes place - = Described action does not take place
MC68HC05B6 Rev. 4.1
RESETS AND INTERRUPTS
Freescale 9-5
9.2
Interrupts
The MCU can be interrupted by four different sources: three maskable hardware interrupts and one non maskable software interrupt: * * * * External signal on the IRQ pin Serial communications interface (SCI) Programmable timer Software interrupt instruction (SWI)
Interrupts cause the processor to save the register contents on the stack and to set the interrupt mask (I-bit) to prevent additional interrupts. The RTI instruction (ReTurn from Interrupt) causes the register contents to be recovered from the stack and normal processing to resume. While executing the RTI instruction, the value of the I-bit is replaced by the corresponding I-bit stored on the stack. Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. The current instruction is the one already fetched and being operated on. When the current instruction is complete, the processor checks all pending hardware interrupts. If interrupts are not masked (I-bit clear) and the corresponding interrupt enable bit is set, the processor proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. Note: Power-on and external reset clear all interrupt enable bits, but set the INTE bit in the miscellaneous register, thus preventing interrupts during the reset sequence.
9
9.2.1
Interrupt priorities
Each potential interrupt source is assigned a priority level, which means that if more than one interrupt is pending at the same time, the processor will service the one with the highest priority first. For example, if both an external interrupt and a timer interrupt are pending after an instruction execution, the external interrupt is serviced first. Table 9-2 shows the relative priority of all the possible interrupt sources. Figure 9-3 shows the interrupt processing flow.
9.2.2
Nonmaskable software interrupt (SWI)
The software interrupt (SWI) is an executable instruction and a nonmaskable interrupt: it is executed regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupts enabled), SWI is executed after interrupts that were pending when the SWI was fetched, but before interrupts
Freescale 9-6
RESETS AND INTERRUPTS
MC68HC05B6 Rev. 4.1
Table 9-2 Interrupt priorities
Source Reset Software interrupt (SWI) External interrupt (IRQ) Timer input captures Timer output compares Timer overflow Serial communications interface (SCI) Register -- -- -- TSR TSR TSR SCSR Flags -- -- -- ICF1, ICF2 OCF1, OCF2 TOF TDRE, TC, OR, RDRF, IDLE Vector address $1FFE, $1FFF $1FFC, $1FFD $1FFA, $1FFB $1FF8, $1FF9 $1FF6, $1FF7 $1FF4, $1FF5 $1FF2, $1FF3 lowest Priority highest
generated after the SWI was fetched. The SWI interrupt service routine address is specified by the contents of memory locations $1FFC and $1FFD.
9.2.3
Maskable hardware interrupts
If the interrupt mask bit in the CCR is set, all maskable interrupts (internal and external) are masked. Clearing the I-bit allows interrupt processing to occur. Note: The internal interrupt latch is cleared in the first part of the interrupt service routine; therefore, one external interrupt pulse could be latched and serviced as soon as the I-bit is cleared.
9.2.3.1
External interrupt (IRQ)
9
If the interrupt mask in the condition code register has been cleared and the interrupt enable bit (INTE) is set and the signal on the external interrupt pin (IRQ) satisfies the condition selected by the option control bits (INTP and INTN), then the external interrupt is recognized. INTE, INTP and INTN are all bits contained in the miscellaneous register at $000C. When the interrupt is recognized, the current state of the CPU is pushed onto the stack and the I-bit is set. This masks further interrupts until the present one is serviced. The external interrupt service routine address is specified by the content of memory locations $1FFA and $1FFB.
MC68HC05B6 Rev. 4.1
RESETS AND INTERRUPTS
Freescale 9-7
Reset
Is I-bit set?
IRQ external interrupt?
Clear IRQ request latch
Stack PC, X, A, CC Timer internal interrupt?
Set I-bit
9
SCI internal interrupt? Load PC from: IRQ: $1FFA-$1FFB Timer IC: $1FF8-$1FF9 Timer OC: $1FF6-$1FF7 Timer OVF:$1FF4-$1FF5 SCI: $1FF2-$1FF3
Fetch next instruction
Execute instruction
Complete interrupt routine and execute RTI
Figure 9-3 Interrupt flow chart
Freescale 9-8
RESETS AND INTERRUPTS
MC68HC05B6 Rev. 4.1
9.2.3.2
Miscellaneous register
Address bit 7 POR bit 6 INTP bit 5 INTN bit 4 INTE bit 3 SFA bit 2 SFB bit 1 SM bit 0 State on reset
Miscellaneous
$000C
WDOG ?001 000?
Note:
The bits shown shaded in the above representation are explained individually in the relevant sections of this manual. The complete register plus an explanation of each bit can be found in Section 3.8.
INTP, INTN -- External interrupt sensitivity options These two bits allow the user to select which edge the IRQ pin is sensitive to as shown in Table 9-3. Both bits can be written to only while the I-bit is set, and are cleared by power-on or external reset. Therefore the device is initialised with negative edge and low level sensitivity.
Table 9-3 IRQ sensitivity
INTP 0 0 1 1 INTN 0 1 0 1 IRQ sensitivity Negative edge and low level sensitive Negative edge only Positive edge only Positive and negative edge sensitive
INTE -- External interrupt enable 1 (set) - External interrupt function (IRQ) enabled. External interrupt function (IRQ) disabled.
9
0 (clear) -
The INTE bit can be written to only while the I-bit is set, and is set by power-on or external reset, thus enabling the external interrupt function. Table 9-3 describes the various triggering options available for the IRQ pin, however it is important to re-emphasize here that in order to avoid any conflict and spurious interrupt, it is only possible to change the external interrupt options while the I-bit is set. Any attempt to change the external interrupt option while the I-bit is clear will be unsuccessful. If an external interrupt is pending, it will automatically be cleared when selecting a different interrupt option. Note: If the external interrupt function is disabled by the INTE bit and an external interrupt is sensed by the edge detector circuitry, then the interrupt request is latched and the interrupt stays pending until the INTE bit is set. The internal latch of the external interrupt is cleared in the first part of the service routine (except for the low level
MC68HC05B6 Rev. 4.1
RESETS AND INTERRUPTS
Freescale 9-9
interrupt which is not latched); therefore, only one external interrupt pulse can be latched during tILIL and serviced as soon as the I-bit is cleared.
9.2.3.3
Timer interrupts
There are five different timer interrupt flags (ICF1, ICF2, OCF1, OCF2 and TOF) that will cause a timer interrupt whenever they are set and enabled. These five interrupt flags are found in the five most significant bits of the timer status register (TSR) at location $0013. ICF1 and ICF2 will vector to the service routine defined by $1FF8-$1FF9, OCF1 and OCF2 will vector to the service routine defined by $1FF6-$1FF7 and TOF will vector to the service routine defined by $1FF4-$1FF5 as shown in Figure 5.1. There are three corresponding enable bits; ICIE for ICF1 and ICF2, OCIE for OCF1 and OCF2, and TOIE for TOF. These enable bits are located in the timer control register (TCR) at address $0012. See Section 5.2.1 and Section 5.2.2 for further information.
9.2.3.4
Serial communications interface (SCI) interrupts
There are five different interrupt flags (TDRE, TC, OR, RDRF and IDLE) that cause SCI interrupts whenever they are set and enabled. These five interrupt flags are found in the five most significant bits of the SCI status register (SCSR) at location $0010. There are four corresponding enable bits: TIE for TDRE, TCIE for TC, RIE for OR and RDRF, and ILIE for IDLE. These enable bits are located in the serial communications control register 2 (SCCR2) at address $000F. See Section 6.11.3 and Section 6.11.4.
9
The SCI interrupt causes the program counter to vector to the address pointed to by memory locations $1FF2 and $1FF3 which contain the starting address of the interrupt service routine. Software in the SCI interrupt service routine must determine the priority and cause of the interrupt by examining the interrupt flags and the status bits located in the serial communications status register SCSR (address $0010). The general sequence for clearing an interrupt is a software sequence of accessing the serial communications status register while the flag is set followed by a read or write of an associated register. Refer to Section 6 for a description of the SCI system and its interrupts.
Freescale 9-10
RESETS AND INTERRUPTS
MC68HC05B6 Rev. 4.1
9.2.4
Hardware controlled interrupt sequence
The following three functions: reset, STOP and WAIT, are not in the strictest sense interrupts. However, they are acted upon in a similar manner. Flowcharts for STOP and WAIT are shown in Figure 2.4. RESET: A reset condition causes the program to vector to its starting address, which is contained in memory locations $1FFE (MSB) and $1FFF (LSB). The I-bit in the condition code register is also set, to disable interrupts. STOP: WAIT: The STOP instruction causes the oscillator to be turned off and the processor to `sleep' until an external interrupt (IRQ) or occurs or the device is reset. The WAIT instruction causes all processor clocks to stop, but leaves the timer clocks running. This `rest' state of the processor can be cleared by reset, an external interrupt (IRQ), a timer interrupt or an SCI interrupt. There are no special WAIT vectors for these individual interrupts.
9
MC68HC05B6 Rev. 4.1
RESETS AND INTERRUPTS
Freescale 9-11
THIS PAGE LEFT BLANK INTENTIONALLY
9
Freescale 9-12
RESETS AND INTERRUPTS
MC68HC05B6 Rev. 4.1
10
CPU CORE AND INSTRUCTION SET
This section provides a description of the CPU core registers, the instruction set and the addressing modes of the MC68HC05B6.
10.1
Registers
The MCU contains five registers, as shown in the programming model of Figure 10-1. The interrupt stacking order is shown in Figure 10-2.
7 7 15 7 0 Accumulator 0 Index register 0 Program counter 15 7 0 0000000011 7 0 111HINZC Stack pointer Condition code register Carry / borrow Zero Negative Interrupt mask Half carry
10
Figure 10-1 Programming model
7 Increasing memory address Return
Unstack
Condition code register Accumulator Index register Program counter high Program counter low
0
Stack Interrupt Decreasing memory address
Figure 10-2 Stacking order
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CPU CORE AND INSTRUCTION SET
Freescale 10-1
10.1.1
Accumulator (A)
The accumulator is a general purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations.
10.1.2
Index register (X)
The index register is an 8-bit register, which can contain the indexed addressing value used to create an effective address. The index register may also be used as a temporary storage area.
10.1.3
Program counter (PC)
The program counter is a 16-bit register, which contains the address of the next byte to be fetched.
10.1.4
Stack pointer (SP)
The stack pointer is a 16-bit register, which contains the address of the next free location on the stack. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to location $00FF. The stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. When accessing memory, the ten most significant bits are permanently set to 0000000011. These ten bits are appended to the six least significant register bits to produce an address within the range of $00C0 to $00FF. Subroutines and interrupts may use up to 64 (decimal) locations. If 64 locations are exceeded, the stack pointer wraps around and overwrites the previously stored information. A subroutine call occupies two locations on the stack; an interrupt uses five locations.
10
10.1.5
Condition code register (CCR)
The CCR is a 5-bit register in which four bits are used to indicate the results of the instruction just executed, and the fifth bit indicates whether interrupts are masked. These bits can be individually tested by a program, and specific actions can be taken as a result of their state. Each bit is explained in the following paragraphs.
Freescale 10-2
CPU CORE AND INSTRUCTION SET
MC68HC05B6 Rev. 4.1
Half carry (H) This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4. Interrupt (I) When this bit is set all maskable interrupts are masked. If an interrupt occurs while this bit is set, the interrupt is latched and remains pending until the interrupt bit is cleared. Negative (N) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. Zero (Z) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero. Carry/borrow (C) When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred during the last arithmetic operation. This bit is also affected during bit test and branch instructions and during shifts and rotates.
10.2
Instruction set
The MCU has a set of 62 basic instructions. They can be grouped into five different types as follows: - - - - - Register/memory Read/modify/write Branch Bit manipulation Control
10
The following paragraphs briefly explain each type. All the instructions within a given type are presented in individual tables. This MCU uses all the instructions available in the M146805 CMOS family plus one more: the unsigned multiply (MUL) instruction. This instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X). The high-order product is then stored in the index register and the low-order product is stored in the accumulator. A detailed definition of the MUL instruction is shown in Table 10-1.
MC68HC05B6 Rev. 4.1
CPU CORE AND INSTRUCTION SET
Freescale 10-3
10.2.1
Register/memory Instructions
Most of these instructions use two operands. The first operand is either the accumulator or the index register. The second operand is obtained from memory using one of the addressing modes. The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register operand. Refer to Table 10-2 for a complete list of register/memory instructions.
10.2.2
Branch instructions
These instructions cause the program to branch if a particular condition is met; otherwise, no operation is performed. Branch instructions are two-byte instructions. Refer to Table 10-3.
10.2.3
Bit manipulation instructions
The MCU can set or clear any writable bit that resides in the first 256 bytes of the memory space (page 0). All port data and data direction registers, timer and serial interface registers, control/status registers and a portion of the on-chip RAM reside in page 0. An additional feature allows the software to test and branch on the state of any bit within these locations. The bit set, bit clear, bit test and branch functions are all implemented with single instructions. For the test and branch instructions, the value of the bit tested is also placed in the carry bit of the condition code register. Refer to Table 10-4.
10.2.4
Read/modify/write instructions
10
These instructions read a memory location or a register, modify or test its contents, and write the modified value back to memory or to the register. The test for negative or zero (TST) instruction is an exception to this sequence of reading, modifying and writing, since it does not modify the value. Refer to Table 10-5 for a complete list of read/modify/write instructions.
10.2.5
Control instructions
These instructions are register reference instructions and are used to control processor operation during program execution. Refer to Table 10-6 for a complete list of control instructions.
10.2.6
Tables
Tables for all the instruction types listed above follow. In addition there is a complete alphabetical listing of all the instructions (see Table 10-7 and Table 10-8), and an opcode map for the instruction set of the M68HC05 MCU family (see Table 10-9).
Freescale 10-4
CPU CORE AND INSTRUCTION SET
MC68HC05B6 Rev. 4.1
Table 10-1 MUL instruction
Operation X:A X*A
Multiplies the eight bits in the index register by the eight Description bits in the accumulator and places the 16-bit result in the concatenated accumulator and index register. Condition codes Source Form Addressing mode Inherent H : Cleared I : Not affected N : Not affected Z : Not affected C : Cleared MUL Cycles 11 Bytes 1 Opcode $42
Table 10-2 Register/memory instructions
Addressing modes Immediate Mnemonic Direct Extended Indexed (no offset) # Cycles Opcode # Bytes Indexed (8-bit offset) # Cycles Opcode # Bytes Indexed (16-bit offset) # Cycles 5 5 6 6 5 5 5 5 5 5 5 5 5 5 4 7 Opcode D6 DE D7 DF DB D9 D0 D2 D4 DA D8 D1 D3 D5 DC DD # Bytes 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
# Cycles
# Cycles
Function Load A from memory Load X from memory Store A in memory Store X in memory Add memory to A Add memory and carry to A Subtract memory Subtract memory from A with borrow AND memory with A OR memory with A Exclusive OR memory with A Arithmetic compare A with memory Arithmetic compare X with memory Bit test memory with A (logical compare) Jump unconditional Jump to subroutine
LDA LDX STA STX ADD ADC SUB SBC AND ORA EOR CMP CPX BIT JMP JSR
A6 AE
2 2
2 2
B6 BE B7 BF
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
3 3 4 4 3 3 3 3 3 3 3 3 3 3 2 5
C6 CE C7 CF CB C9 C0 C2 C4 CA C8 C1 C3 C5 CC CD
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
# Cycles 4 4 5 5 4 4 4 4 4 4 4 4 4 4 3 6
Opcode
Opcode
Opcode
# Bytes
# Bytes
# Bytes
F6 FE F7 FF FB F9 F0 F2 F4 FA F8 F1 F3 F5 FC FD
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
3 3 4 4 3 3 3 3 3 3 3 3 3 3 2 5
E6 EE E7 EF EB E9 E0 E2 E4 EA E8 E1 E3 E5 EC ED
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
4 4 5 5 4 4 4 4 4 4 4 4 4 4 3 6
AB A9 A0 A2 A4 AA A8 A1 A3 A5
2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2
BB B9 B0 B2 B4 BA B8 B1 B3 B5 BC BD
10
MC68HC05B6 Rev. 4.1
CPU CORE AND INSTRUCTION SET
Freescale 10-5
Table 10-3 Branch instructions
Relative addressing mode Function Branch always Branch never Branch if higher Branch if lower or same Branch if carry clear (Branch if higher or same) Branch if carry set (Branch if lower) Branch if not equal Branch if equal Branch if half carry clear Branch if half carry set Branch if plus Branch if minus Branch if interrupt mask bit is clear Branch if interrupt mask bit is set Branch if interrupt line is low Branch if interrupt line is high Branch to subroutine Mnemonic BRA BRN BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BHCC BHCS BPL BMI BMC BMS BIL BIH BSR Opcode # Bytes # Cycles 20 21 22 23 24 24 25 25 26 27 28 29 2A 2B 2C 2D 2E 2F AD 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 6
Table 10-4 Bit manipulation instructions
Addressing Modes
10
Bit set/clear Function Branch if bit n is set Branch if bit n is clear Set bit n Clear bit n Mnemonic BRSET n (n=0-7) BRCLR n (n=0-7) BSET n (n=0-7) BCLR n (n=0-7) 10+2*n 11+2*n 2 2 5 5
Bit test and branch 2*n 01+2*n 3 3 5 5
Opcode # Bytes # Cycles Opcode # Bytes # Cycles
Freescale 10-6
CPU CORE AND INSTRUCTION SET
MC68HC05B6 Rev. 4.1
Table 10-5 Read/modify/write instructions
Addressing modes Inherent (A) Mnemonic # Cycles Opcode Inherent (X) # Cycles Opcode Opcode Direct Indexed (no offset) # Cycles # Cycles Opcode # Bytes Indexed (8-bit offset) # Cycles 6 6 6 6 6 6 6 6 6 6 5 Opcode 6C 6A 6F 63 60 69 66 68 64 67 6D # Bytes 2 2 2 2 2 2 2 2 2 2 2
# Bytes
# Bytes
Function Increment Decrement Clear Complement Negate (two's complement) Rotate left through carry Rotate right through carry Logical shift left Logical shift right Arithmetic shift right Test for negative or zero Multiply
INC DEC CLR COM NEG ROL ROR LSL LSR ASR TST MUL
4C 4A 4F 43 40 49 46 48 44 47 4D 42
1 1 1 1 1 1 1 1 1 1 1 1
3 3 3 3 3 3 3 3 3 3 3 11
5C 5A 5F 53 50 59 56 58 54 57 5D
1 1 1 1 1 1 1 1 1 1 1
3 3 3 3 3 3 3 3 3 3 3
3C 3A 3F 33 30 39 36 38 34 37 3D
# Bytes 2 2 2 2 2 2 2 2 2 2 2
5 5 5 5 5 5 5 5 5 5 4
7C 7A 7F 73 70 79 76 78 74 77 7D
1 1 1 1 1 1 1 1 1 1 1
5 5 5 5 5 5 5 5 5 5 4
Table 10-6 Control instructions
Inherent addressing mode Function Transfer A to X Transfer X to A Set carry bit Clear carry bit Set interrupt mask bit Clear interrupt mask bit Software interrupt Return from subroutine Return from interrupt Reset stack pointer No-operation Stop Wait Mnemonic TAX TXA SEC CLC SEI CLI SWI RTS RTI RSP NOP STOP WAIT Opcode # Bytes # Cycles 97 9F 99 98 9B 9A 83 81 80 9C 9D 8E 8F 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 10 6 9 2 2 2 2
10
MC68HC05B6 Rev. 4.1
CPU CORE AND INSTRUCTION SET
Freescale 10-7
Table 10-7 Instruction set (1 of 2)
Addressing modes INH IMM DIR EXT REL IX IX1 IX2 BSC BTB H * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Address mode abbreviations
BSC Bit set/clear BTB DIR EXT INH Bit test & branch Direct Extended Inherent IMM IX IX1 IX2 REL Immediate Indexed (no offset) Indexed, 1 byte offset Indexed, 2 byte offset Relative H I N Z C Not implemented
Mnemonic ADC ADD AND ASL ASR BCC BCLR BCS BEQ BHCC BHCS BHI BHS BIH BIL BIT BLO BLS BMC BMI BMS BNE BPL BRA
Condition codes I * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 0 * * N * * * * * * * * * * * * * * * * * * * * * * * * * 0 Z * * * * * * * * * * * * * * * * * * * * * * * * * 1 C * * * * * * * * * * * * * * * * * * * * * * * 0 * *
10
BRN BRCLR BRSET BSET BSR CLC CLI CLR CMP
Condition code symbols
Half carry (from bit 3) Interrupt mask Negate (sign bit) Zero Carry/borrow * ? 0 1 Tested and set if true, cleared otherwise Not affected Load CCR from stack Cleared Set
Freescale 10-8
CPU CORE AND INSTRUCTION SET
MC68HC05B6 Rev. 4.1
Table 10-8 Instruction set (2 of 2)
Addressing modes INH IMM DIR EXT REL IX IX1 IX2 BSC BTB H * * * * * * * * * * * 0 * * * * * * ? * * * * * * * * * * * * *
Address mode abbreviations
BSC Bit set/clear BTB DIR EXT INH Bit test & branch Direct Extended Inherent IMM IX IX1 IX2 REL Immediate Indexed (no offset) Indexed, 1 byte offset Indexed, 2 byte offset Relative H I N Z C Not implemented
Mnemonic COM CPX DEC EOR INC JMP JSR LDA LDX LSL LSR MUL NEG NOP ORA ROL ROR RSP RTI RTS SBC SEC SEI STA STOP STX SUB SWI TAX TST TXA WAIT
Condition codes I * * * * * * * * * * * * * * * * * * ? * * * 1 * 0 * * 1 * * * 0 N * * 0 * * * ? * * * * * * * * Z * * * * * ? * * * * * * * * C 1 * * * * * * * 0 * * * ? * 1 * * * * * * * * *
10
Condition code symbols
Half carry (from bit 3) Interrupt mask Negate (sign bit) Zero Carry/borrow * ? 0 1 Tested and set if true, cleared otherwise Not affected Load CCR from stack Cleared Set
MC68HC05B6 Rev. 4.1
CPU CORE AND INSTRUCTION SET
Freescale 10-9
10
Freescale 10-10
High
High Low
3 IX 3 IX 3 IX 3 3 REL 2 3 REL 3 REL 3 REL 2 3 REL 2 3 REL 3 REL 2 3 REL 2 3 2 1 1
Low
Bit manipulation BTB BSC 0 1 0000 0001 DIR 3 0011 NEG
DIR 1 INH 1 INH 2 IX1 1 IX 1 5
Branch REL 2 0010 INH 4 0100 NEGA RTS
INH 2 2 INH 6 2 3
Read/modify/write INH IX1 5 6 0101 0110 IX 7 0111
6
Control INH INH 8 9 1000 1001 IMM A 1010 SUB CMP SBC CPX AND BIT LDA
IMM 2 2 IMM 2 2 IMM 2 2 IMM 2 2 IMM 2 2 IMM 2 2 IMM 2 2 2
DIR B 1011 SUB CMP SBC CPX AND BIT LDA STA EOR ADC ORA ADD
2 DIR 3 3 DIR 3 3 DIR 3 3 DIR 3 2 DIR 3 3 DIR 3 4 DIR 3 3 DIR 3 3 DIR 3 3 DIR 3 3 DIR 3 3 DIR 3 3 3
Register/memory EXT IX2 C D 1100 1101 IX1 E 1110
5 IX2 2 5
IX F 1111
4 IX1 1 4
3
BRSET0 CMP SBC CPX AND BIT LDA STA EOR ADC ORA ADD JMP BSR
2 6 REL 2 2 DIR 3 5 EXT 3 5 EXT 3 4 EXT 3 4 EXT 3 4 EXT 3 4 EXT 3 3 EXT 3 4 EXT 3 4 EXT 3 4 EXT 3 4 EXT 3 4 EXT 3 4
5
3
BRCLR0 MUL COMA LSRA
INH 1 INH 2 IX1 1 IX 2 INH 1 3 INH 3 11
BTB 2 5
BSET0 CMP SBC CPX AND BIT LDA STA EOR ADC ORA ADD JMP JSR LDX TXA
2 INH 2 IMM 2 EXT 3 6 IX2 2 5 IX2 2 5 IX2 2 6 IX2 2 5 IX2 2 5 IX2 2 5 IX2 2 5 IX2 2 4 IX2 2 5 IX2 2 5 IX2 2 5
5
3
BRSET1 COM LSR
DIR 1 DIR 1 5 5
BTB 2 5
BCLR0 SBC CPX AND BIT LDA STA EOR ADC ORA ADD JMP JSR LDX STX
DIR 3 3 DIR 3 4 DIR 3 IX2 2 7 IX1 1 4 IX1 1 4 IX1 1 4 IX1 1 4 IX1 1 5 IX1 1 4 IX1 1 4 IX1 1 4 IX1 1 4 IX1 1 3 IX1 1 4
BSC 2 5
BRA CMP SBC CPX AND BIT LDA STA EOR ADC ORA ADD JMP JSR LDX STX
EXT 3 4 EXT 3 5 EXT 3 IX1 1 6
NEGX CMP
3
NEG
NEG
5
RTI
9
SUB
4
SUB
SUB
SUB
3
BRCLR1 LSRX
INH 2 3
BTB 2 5
BSET1 COMX LSR
IX1 1 6 3
BSC 2 5 6 5 IX 1 5 10 INH 2
BRN
3
BRSET2
BTB 2 5
BCLR1 LSR
BSC 2 5
BHI COM COM SWI
3
BRCLR2 ROR ASR LSL ROL DEC
DIR 1 1 INH 1 INH 2 IX1 1 IX 1 DIR 1 5 DIR 1 5 DIR 1 5 DIR 1 5 5
BTB 2 5 3 3 6 IX1 1 6 IX1 1 6 IX1 1 6 IX1 1 6 5 IX 5 IX 5 IX 5 IX 5 1 1 1 2 2 INH 2 INH 2 2 INH 2 2 INH 2 2 2 IMM 2 2 IMM 2 2 IMM 2 2 IMM 2
BSET2
BSC 2 5
BLS
3
BRSET3 ASRA LSLA ROLA DECA SEI RSP NOP
INH 2 INH 2 INH 2 2 INH 1 3 INH 1 3 INH 1 3 INH 1 3
BTB 2 5
BCLR2 RORA ASRX LSLX ROLX DECX ADD
INH 2 3 INH 2 3 INH 2 3 INH 2 3
BSC 2 5
BCC
IX 3 IX 3 IX 3 IX 4 IX 3 IX 3 IX 3 IX 3 IX 2
3 REL 2 3
BRCLR3 LSL ROL DEC DEC CLI ORA ROL SEC ADC LSL CLC EOR
BTB 2 5
BSET3 ASR ASR TAX
BSC 2 5
BCS RORX ROR ROR
3 REL 2 3
BRSET4
BTB 2 5
BCLR3
BSC 2 5
BNE
3 REL 2 3 REL 3 REL 2 3 REL 2 3 REL 3 REL 2 1 5 DIR 1 4 DIR 1 3 INH 1 3 INH 1 3 INH 2 3 INH 2 6 IX1 1 5 IX1 1 5 IX 4 IX 1 2 1
BRCLR4
BTB 2 5
BSET4
BSC 2 5
BEQ
3
BRSET5
BTB 2 5
BCLR4
BSC 2 5
BHCC
3
BRCLR5 INC TST STOP WAIT
INH 2 INH 1
BTB 2 5
BSET5
BSC 2 5
BHCS
3
BRSET6 TSTA TSTX TST TST
BTB 2 5
BCLR5 INCA INCX INC INC
BSC 2 5
BPL
3
BRCLR6
BTB 2 5
BSET6
BSC 2 5
BMI
Table 10-9 M68HC05 opcode map
3
BRSET7 CLR
DIR 1 INH 1 INH 2 IX1 1 IX 1 5
BTB 2 5 3 3 6 5
BCLR6
BSC 2 5
BMC
JMP
IX2 2 5
CPU CORE AND INSTRUCTION SET
LDX STX CLRA CLRX CLR CLR
IX2 2 6 IX2 2
0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111 JSR LDX STX
IX1 1 4 IX1 1 5 IX1 1
3
BRCLR7
BTB 2 5
BSET7
BSC 2 5
BMS
JSR LDX STX
IX 5 IX 3 IX 4 IX
BTB 2
BCLR7
BSC 2 5
BIL
BSC 2
BIH
0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111
Abbreviations for address modes and registers
Legend F 1111 Mnemonic
1
Opcode in hexadecimal Opcode in binary SUB Not implemented Bytes Cycles
3 IX
BSC BTB DIR EXT INH IMM IX IX1 IX2 REL A X Indexed (no offset) Indexed, 1 byte (8-bit) offset Indexed, 2 byte (16-bit) offset Relative Accumulator Index register
Bit set/clear Bit test and branch Direct Extended Inherent Immediate
0 0000 Address mode
MC68HC05B6 Rev. 4.1
10.3
Addressing modes
Ten different addressing modes provide programmers with the flexibility to optimize their code for all situations. The various indexed addressing modes make it possible to locate data tables, code conversion tables and scaling tables anywhere in the memory space. Short indexed accesses are single byte instructions; the longest instructions (three bytes) enable access to tables throughout memory. Short absolute (direct) and long absolute (extended) addressing are also included. One or two byte direct addressing instructions access all data bytes in most applications. Extended addressing permits jump instructions to reach all memory locations. The term `effective address' (EA) is used in describing the various addressing modes. The effective address is defined as the address from which the argument for an instruction is fetched or stored. The ten addressing modes of the processor are described below. Parentheses are used to indicate `contents of' the location or register referred to. For example, (PC) indicates the contents of the location pointed to by the PC (program counter). An arrow indicates `is replaced by' and a colon indicates concatenation of two bytes. For additional details and graphical illustrations, refer to the M6805 HMOS/M146805 CMOS Family Microcomputer/ Microprocessor User's Manual or to the M68HC05 Applications Guide.
10.3.1
Inherent
In the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. Operations specifying only the index register or accumulator, as well as the control instruction, with no other arguments are included in this mode. These instructions are one byte long.
10.3.2
Immediate
In the immediate addressing mode, the operand is contained in the byte immediately following the opcode. The immediate addressing mode is used to access constants that do not change during program execution (e.g. a constant used to initialize a loop counter). EA = PC+1; PC PC+2
10
10.3.3
Direct
In the direct addressing mode, the effective address of the argument is contained in a single byte following the opcode byte. Direct addressing allows the user to directly address the lowest 256 bytes in memory with a single two-byte instruction. EA = (PC+1); PC PC+2 Address bus high 0; Address bus low (PC+1)
MC68HC05B6 Rev. 4.1
CPU CORE AND INSTRUCTION SET
Freescale 10-11
10.3.4
Extended
In the extended addressing mode, the effective address of the argument is contained in the two bytes following the opcode byte. Instructions with extended addressing mode are capable of referencing arguments anywhere in memory with a single three-byte instruction. When using the Freescale assembler, the user need not specify whether an instruction uses direct or extended addressing. The assembler automatically selects the short form of the instruction. EA = (PC+1):(PC+2); PC PC+3 Address bus high (PC+1); Address bus low (PC+2)
10.3.5
Indexed, no offset
In the indexed, no offset addressing mode, the effective address of the argument is contained in the 8-bit index register. This addressing mode can access the first 256 memory locations. These instructions are only one byte long. This mode is often used to move a pointer through a table or to hold the address of a frequently referenced RAM or I/O location. EA = X; PC PC+1 Address bus high 0; Address bus low X
10.3.6
Indexed, 8-bit offset
In the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the unsigned byte following the opcode. Therefore the operand can be located anywhere within the lowest 511 memory locations. This addressing mode is useful for selecting the mth element in an n element table.
10
10.3.7
EA = X+(PC+1); PC PC+2 Address bus high K; Address bus low X+(PC+1) where K = the carry from the addition of X and (PC+1)
Indexed, 16-bit offset
In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the two unsigned bytes following the opcode. This address mode can be used in a manner similar to indexed, 8-bit offset except that this three-byte instruction allows tables to be anywhere in memory. As with direct and extended addressing, the Freescale assembler determines the shortest form of indexed addressing. EA = X+[(PC+1):(PC+2)]; PC PC+3 Address bus high (PC+1)+K; Address bus low X+(PC+2) where K = the carry from the addition of X and (PC+2)
Freescale 10-12
CPU CORE AND INSTRUCTION SET
MC68HC05B6 Rev. 4.1
10.3.8
Relative
The relative addressing mode is only used in branch instructions. In relative addressing, the contents of the 8-bit signed byte (the offset) following the opcode are added to the PC if, and only if, the branch conditions are true. Otherwise, control proceeds to the next instruction. The span of relative addressing is from -126 to +129 from the opcode address. The programmer need not calculate the offset when using the Freescale assembler, since it calculates the proper offset and checks to see that it is within the span of the branch. EA = PC+2+(PC+1); PC EA if branch taken; otherwise EA = PC PC+2
10.3.9
Bit set/clear
In the bit set/clear addressing mode, the bit to be set or cleared is part of the opcode. The byte following the opcode specifies the address of the byte in which the specified bit is to be set or cleared. Any read/write bit in the first 256 locations of memory, including I/O, can be selectively set or cleared with a single two-byte instruction. EA = (PC+1); PC PC+2 Address bus high 0; Address bus low (PC+1)
10.3.10
Bit test and branch
The bit test and branch addressing mode is a combination of direct addressing and relative addressing. The bit to be tested and its condition (set or clear) is included in the opcode. The address of the byte to be tested is in the single byte immediately following the opcode byte (EA1). The signed relative 8-bit offset in the third byte (EA2) is added to the PC if the specified bit is set or cleared in the specified memory location. This single three-byte instruction allows the program to branch based on the condition of any readable bit in the first 256 locations of memory. The span of branch is from -125 to +130 from the opcode address. The state of the tested bit is also transferred to the carry bit of the condition code register. EA1 = (PC+1); PC PC+2 Address bus high 0; Address bus low (PC+1) EA2 = PC+3+(PC+2); PC EA2 if branch taken; otherwise PC PC+3
10
MC68HC05B6 Rev. 4.1
CPU CORE AND INSTRUCTION SET
Freescale 10-13
THIS PAGE LEFT BLANK INTENTIONALLY
10
Freescale 10-14
CPU CORE AND INSTRUCTION SET
MC68HC05B6 Rev. 4.1
11
ELECTRICAL SPECIFICATIONS
This section contains the electrical specifications and associated timing information for the MC68HC05B6.
11.1
Absolute maximum ratings
Table 11-1 Absolute maximum ratings
Rating Supply voltage(1) Input voltage (Except VPP1) Input voltage - Self-check mode (IRQ pin only) Operating temperature range - Standard (MC68HC05B6) - Extended (MC68HC05B6C) - Automotive (MC68HC05B6M) Storage temperature range Current drain per pin (excluding VDD and VSS)(2) - Source - Sink (1) All voltages are with respect to VSS. (2) Maximum current drain per pin is for one pin at a time, limited by an external resistor. Symbol VDD VIN VIN TA Value - 0.5 to +7.0 VSS - 0.5 to VDD + 0.5 VSS - 0.5 to 2VDD + 0.5 TL to TH 0 to +70 -40 to +85 -40 to +125 - 65 to +150 25 45 Unit V V V
C C mA mA
TSTG ID IS
11
Note:
This device contains circuitry designed to protect against damage due to high electrostatic voltages or electric fields. However, it is recommended that normal precautions be taken to avoid the application of any voltages higher than those given in the maximum ratings table to this high impedance circuit. For maximum reliability all unused inputs should be tied to either VSS or VDD.
MC68HC05B6 Rev. 4.1
ELECTRICAL SPECIFICATIONS
Freescale 11-1
11.2
DC electrical characteristics
Table 11-2 DC electrical characteristics for 5V operation
11
(VDD = 5 Vdc 10%, VSS = 0 Vdc, TA = TL to TH) Characteristic(1) Output voltage ILOAD = - 10 A ILOAD = +10 A Output high voltage (ILOAD = 0.8mA) PA0-7, PB0-7, PC0-7, TCMP1, TCMP2 Output high voltage (ILOAD = 1.6mA) TDO, SCLK, PLMA, PLMB Output low voltage (ILOAD = 1.6mA) PA0-7, PB0-7, PC0-7, TCMP1, TCMP2, TDO, SCLK, PLMA, PLMB Output low voltage (ILOAD = 1.6mA) RESET Input high voltage PA0-7, PB0-7, PC0-7, PD0-7, OSC1, IRQ, RESET, TCAP1, TCAP2, RDI Input low voltage PA0-7, PB0-7, PC0-7, PD0-7, OSC1, IRQ, RESET,TCAP1, TCAP2, RDI Supply current(3) RUN (SM = 0) (See Figure 11-1) RUN (SM = 1) (See Figure 11-2) WAIT (SM = 0) (See Figure 11-3) WAIT (SM = 1) (See Figure 11-4) STOP 0 to 70 (standard) - 40 to 85 (extended) - 40 to 105 (extended) - 40 to 125 (automotive) High-Z leakage current PA0-7, PB0-7, PC0-7, TDO, RESET, SCLK Input current (0 to 70) IRQ, OSC1, TCAP1, TCAP2, RDI, PD0/AN0-PD7/AN7 (channel not selected) Input current (- 40 to 125) IRQ, OSC1, TCAP1, TCAP2, RDI, Capacitance Ports (as input or output), RESET, TDO, SCLK IRQ, TCAP1, TCAP2, OSC1, RDI PD0/AN0-PD7/AN7 (A/D off) PD0/AN0-PD7/AN7 (A/D on)
Symbol VOH VOL VOH VOH VOL VOL VIH VIL
Min VDD - 0.1 -- VDD - 0.8 VDD - 0.8 --
Typ(2) -- -- VDD - 0.4 VDD - 0.4 0.1 0.4
Max -- 0.1 -- -- 0.4 1 VDD 0.2VDD 6 1.5 2 1 10 20 60 60 1 1 1 5 12 8 -- --
Unit V
V
V
0.7VDD VSS -- -- -- -- -- -- -- --
--
V
--
V
IDD
3.5 0.5 1 0.35 2 -- -- -- 0.2 0.2 0.2 -- -- -- 12 22
mA mA mA mA A A A A A mA A pF pF pF pF
IIL IIN IIN COUT CIN CIN CIN
-- --
-- -- -- -- --
(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switching currents inherent in CMOS designs (see Section 2). (2) Typical values are at mid point of voltage range and at 25C only. (3) RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 4.2MHz); all inputs 0.2 V from rail; no DC loads; maximum load on outputs 50pF (20pF on OSC2). STOP /WAIT IDD: all ports configured as inputs; VIL = 0.2 V and VIH = VDD - 0.2 V: STOP IDD measured with OSC1 = VDD. WAIT IDD is affected linearly by the OSC2 capacitance.
Freescale 11-2
ELECTRICAL SPECIFICATIONS
MC68HC05B6 Rev. 4.1
11.2.1
IDD trends for 5V operation
For the examples below, typical values are at the mid-point of the voltage range and at a temperature of 25C only.
8 7 6 5 4 3 2 1 0 0 0.5 1 1.5 2 2.5 3 Internal operating frequency (MHz) 3.5 4
IDD (mA)
5.5V 4.5V
Figure 11-1 Run IDD vs internal operating frequency (4.5V, 5.5V)
1.2 1 0.8 IDD (mA) 0.6 0.4 0.2 0 0 0.5 1 1.5 2 2.5 3 Internal operating frequency (MHz) 3.5 4 5.5V 4.5V
Figure 11-2 Run IDD (SM = 1) vs internal operating frequency (4.5V, 5.5V)
2.5 2 IDD (mA) 1.5 1 0.5 0 0 0.5 1 1.5 2 2.5 3 Internal operating frequency (MHz) 3.5 4 5.5V 4.5V
11
Figure 11-3 Wait IDD vs internal operating frequency (4.5V, 5.5V)
MC68HC05B6 Rev. 4.1
ELECTRICAL SPECIFICATIONS
Freescale 11-3
0.9 0.8 0.7 0.6 0.5 IDD (mA) 0.4 0.3 0.2 0.1 0 0 0.5 1 1.5 2 2.5 3 Internal operating frequency (MHz) 3.5 4
5.5V 4.5V
Figure 11-4 Wait IDD (SM = 1) vs internal operating frequency (4.5V, 5.5V)
1.6 1.4 1.2 1 0.8 IDD (mA) 0.6 0.4 0.2 0 0 0.5 1 1.5 2 Internal operating frequency (MHz) 2.5 3
A/D + SCI A/D SCI
Figure 11-5 Increase in IDD vs frequency for A/D, SCI systems active, VDD = 5.5V
11
IDD (mA)
8 7 6 5 4 3 2 1 0
Run IDD Wait IDD Run IDD (SM = 1) Wait IDD (SM = 1)
0
0.5
1
1.5 2 2.5 3 Internal operating frequency (MHz)
3.5
4
Figure 11-6 IDD vs mode vs internal operating frequency, VDD = 5.5V
Freescale 11-4
ELECTRICAL SPECIFICATIONS
MC68HC05B6 Rev. 4.1
Table 11-3 DC electrical characteristics for 3.3V operation
(VDD = 3.3Vdc 10%, VSS = 0Vdc, TA = TL to TH) Characteristic(1) Symbol Output voltage ILOAD = - 10 A VOH ILOAD = +10 A VOL Output high voltage (ILOAD = 0.2mA) PA0-7, PB0-7, PC0-7, TCMP1, TCMP2 VOH Output high voltage (ILOAD = 0.4mA) TDO, SCLK, PLMA, PLMB VOH Output low voltage (ILOAD = 0.4mA) PA0-7, PB0-7, PC0-7, TCMP1, TCMP2, VOL TDO, SCLK, PLMA, PLMB Output low voltage (ILOAD = 0.4mA) VOL RESET Input high voltage PA0-7, PB0-7, PC0-7, PD0-7, OSC1, VIH IRQ, RESET, TCAP1, TCAP2, RDI Input low voltage PA0-7, PB0-7, PC0-7, PD0-7, OSC1, IRQ, VIL RESET, TCAP1, TCAP2, RDI Supply current(3) RUN (SM = 0) (See Figure 11-1) RUN (SM = 1) (See Figure 11-2) WAIT (SM = 0) (See Figure 11-3) WAIT (SM = 1) (See Figure 11-4) IDD STOP 0 to 70 (standard) - 40 to 85 (extended) - 40 to 105 (extended) - 40 to 125 (automotive) High-Z leakage current PA0-7, PB0-7, PC0-7, TDO, RESET, SCLK IIL Input current (0 to 70) IRQ, OSC1, TCAP1, TCAP2, RDI, IIN PD0/AN0-PD7/AN7 (channel not selected) Input current (- 40 to 125) IRQ, OSC1, TCAP1, TCAP2, RDI, IIN Capacitance Ports (as input or output), RESET, TDO, COUT SCLK CIN IRQ, TCAP1, TCAP2, OSC1, RDI CIN PD0/AN0-PD7/AN7 (A/D off) CIN PD0/AN0-PD7/AN7 (A/D on) Min VDD - 0.1 -- VDD - 0.3 VDD - 0.3 -- Typ(2) -- -- VDD - 0.1 VDD - 0.1 0.1 0.2 0.7VDD VSS -- -- -- -- -- -- -- -- -- -- -- Max -- 0.1 -- -- 0.3 0.6 VDD 0.2VDD 3 1 1.5 0.5 10 10 40 40 1 1 1 5 12 8 -- -- V Unit V
V
V
--
V
1.2 0.2 0.4 0.15 1 -- -- -- 0.2 0.2 0.2 -- -- -- 12 22
mA mA mA mA A A A A A A A pF pF pF pF
-- -- -- -- --
11
(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switching currents inherent in CMOS designs (see Section 2). (2) Typical values are at mid point of voltage range and at 25C only. (3) RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 2.0MHz); all inputs 0.2 V from rail; no DC loads; maximum load on outputs 50pF (20pF on OSC2). STOP /WAIT IDD: all ports configured as inputs; VIL = 0.2 V and VIH = VDD - 0.2 V: STOP IDD measured with OSC1 = VDD. WAIT IDD is affected linearly by the OSC2 capacitance.
MC68HC05B6 Rev. 4.1
ELECTRICAL SPECIFICATIONS
Freescale 11-5
11.2.2
IDD trends for 3.3V operation
For the examples below, typical values are at the mid-point of the voltage range and at a temperature of 25C only.
2.5 2 IDD (mA) 1.5 1 0.5 0 0 0.5 1 1.5 2 Internal operating frequency (MHz) 2.5 3.6V 3.0V
Figure 11-7 Run IDD vs internal operating frequency (3 V, 3.6V)
0.6 0.5 0.4 IDD (mA) 0.3 0.2 0.1 0 0 0.5 1 1.5 2 Internal operating frequency (MHz) 2.5 3.6V 3.0V
Figure 11-8 Run IDD (SM = 1) vs internal operating frequency (3V,3.6V)
11
1.2 1 0.8 IDD (mA) 0.6 0.4 0.2 0 0 0.5 1 1.5 2 Internal operating frequency (MHz) 2.5 3.6V 3.0V
Figure 11-9 Wait IDD vs internal operating frequency (3V, 3.6V)
Freescale 11-6
ELECTRICAL SPECIFICATIONS
MC68HC05B6 Rev. 4.1
0.5 0.4 IDD (mA) 0.3 0.2 0.1 0 0 0.5 1 1.5 2 Internal operating frequency (MHz) 2.5 3.6V 3.0V
Figure 11-10 Wait IDD (SM = 1) vs internal operating frequency (3V, 3.6V)
0.7 0.6 0.5 IDD (mA) 0.4 0.3 0.2 0.1 0
A/D + SCI A/D SCI
0
0.5
1 1.5 2 Internal operating frequency (MHz)
2.5
Figure 11-11 Increase in IDD vs frequency for A/D, SCI systems active, VDD = 3.6V
2.5 2 IDD (mA) 1.5 1 0.5 0 0 0.5 1 1.5 Internal operating frequency (MHz) 2 2.5 Run IDD Wait IDD Run IDD (SM=1) Wait IDD (SM=1)
11
Figure 11-12 IDD vs mode vs internal operating frequency, VDD = 3.6V
MC68HC05B6 Rev. 4.1
ELECTRICAL SPECIFICATIONS
Freescale 11-7
11.3
A/D converter characteristics
Table 11-4 A/D characteristics for 5V operation
(VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH) Characteristic Resolution Non-linearity Parameter Number of bits resolved by the A/D Max deviation from the best straight line through the A/D transfer characteristics (VRH = VDD and VRL = 0V) Uncertainty due to converter resolution Difference between the actual input voltage and the full-scale equivalent of the binary code output code for all errors Analog input voltage range Maximum analog reference voltage Minimum analog reference voltage Minimum difference between VRH and VRL Total time to perform a single analog to digital conversion a. External clock (OSC1, OSC2) b. Internal RC oscillator Conversion result never decreases with an increase in input voltage and has no missing codes Conversion result when VIN = VRL Conversion result when VIN = VRH 00 -- -- -- -- -- Min 8 -- -- -- VRL VRL VSS - 0.1 3 -- -- Max -- 0.5 0.5 1 VRH VDD + 0.1 VRH -- 32 32 GUARANTEED -- FF 12 12 12 1 Hex Hex tCYC s pF A Unit Bit LSB LSB LSB V V V V tCYC s
Quantization error Absolute accuracy
Conversion range VRH VR(1) Conversion time VRL
Monotonicity Zero input reading Full scale reading
Sample acquisition time Analog input acquisition sampling a. External clock (OSC1, OSC2) b. Internal RC oscillator(2) Sample/hold capacitance Input capacitance on PD0/AN0-PD7/AN7 Input leakage(3) Input leakage on A/D pins PD0/AN0-PD7/AN7, VRL, VRH
(1) Performance verified down to 2.5V VR, but accuracy is tested and guaranteed at VR = 5V10%.
11
(2) Source impedances greater than 10k will adversely affect internal charging time during input sampling. (3) The external system error caused by input leakage current is approximately equal to the product of R source and input current. Input current to A/D channel will be dependent on external source impedance (see Figure 8-2).
Freescale 11-8
ELECTRICAL SPECIFICATIONS
MC68HC05B6 Rev. 4.1
Table 11-5 A/D characteristics for 3.3V operation
(VDD = 3.3 Vdc 10%, VSS = 0 Vdc, TA = TL to TH) Characteristic Resolution Non-linearity Parameter Number of bits resolved by the A/D Max deviation from the best straight line through the A/D transfer characteristics (VRH = VDD and VRL = 0V) Uncertainty due to converter resolution Difference between the actual input voltage and the full-scale equivalent of the binary code output code for all errors Analog input voltage range Maximum analog reference voltage Minimum analog reference voltage Minimum difference between VRH and VRL Total time to perform a single analog to digital conversion Internal RC oscillator Conversion result never decreases with an increase in input voltage and has no missing codes Conversion result when VIN = VRL Conversion result when VIN = VRH 00 -- -- -- -- Min 8 -- -- -- VRL VRL VSS - 0.1 3 -- Max -- 1 1 2 VRH VDD + 0.1 VRH -- 32 GUARANTEED -- FF 12 12 1 Hex Hex s pF A Unit Bit LSB LSB LSB V V V V s
Quantization error Absolute accuracy
Conversion range VRH VRL VR Conversion time Monotonicity Zero input reading Full scale reading
Sample acquisition time Analog input acquisition sampling Internal RC oscillator(1) Sample/hold capacitance Input capacitance on PD0/AN0-PD7/AN7 Input leakage(2) Input leakage on A/D pins PD0/AN0-PD7/AN7, VRL, VRH
(1) Source impedances greater than 10k will adversely affect internal charging time during input sampling. (2) The external system error caused by input leakage current is approximately equal to the product of R source and input current. Input current to A/D channel will be dependent on external source impedance (see Figure 8-2).
11
MC68HC05B6 Rev. 4.1
ELECTRICAL SPECIFICATIONS
Freescale 11-9
11.4
Control timing
Table 11-6 Control timing for 5V operation
(VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH) Characteristic Symbol Frequency of operation Crystal option fOSC External clock option fOSC Internal operating frequency (fOSC/2) Using crystal fOP Using external clock fOP Cycle time (see Figure 9-1) tCYC Crystal oscillator start-up time (see Figure 9-1) tOXOV Stop recovery start-up time (crystal oscillator) tILCH RC oscillator stabilization time tADRC A/D converter stabilization time tADON External RESET input pulse width tRL Power-on RESET output pulse width 4064 cycle tPORL 16 cycle tPORL Watchdog RESET output pulse width tDOGL Watchdog time-out tDOG EEPROM byte erase time 0 to 70 (standard) - 40 to 85 (extended) - 40 to 125 (automotive) EEPROM byte program time(1) 0 to 70 (standard) - 40 to 85 (extended) - 40 to 125 (automotive) Timer (see Figure 11-13) Resolution(2) Input capture pulse width Input capture pulse period Interrupt pulse width (edge-triggered) Interrupt pulse period OSC1 pulse width(5) Write/Erase endurance(6)(7) Data retention(6)(7) tERA tERA tERA tPROG tPROG tPROG tRESL tTH, tTL tTLTL tILIH tILIL tOH, tOL -- -- Min -- dc dc dc 476 -- Max 4.2 4.2 2.1 2.1 -- 100 100 5 500 -- -- -- -- 7168 -- -- -- -- -- -- -- -- -- -- -- -- Unit MHz MHz MHz MHz ns ms ms s s tCYC tCYC tCYC tCYC tCYC ms ms ms ms ms ms tCYC ns tCYC ns tCYC ns cycles years
1.5 4064 16 1.5 6144 10 10 10 10 10 20 4 125 --(3) 125 --(4) 90 10000 10
11
(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when programming the EEPROM. (2) Since a 2-bit prescaler in the timer must count four external cycles (tCYC), this is the limiting factor in determining the timer resolution. (3) The minimum period tTLTL should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 tCYC. (4) The minimum period tILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 tCYC. (5) tOH and tOL should not total less than 238ns. (6) At a temperature of 85C (7) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information.
Freescale 11-10
ELECTRICAL SPECIFICATIONS
MC68HC05B6 Rev. 4.1
Table 11-7 Control timing for 3.3V operation
(VDD = 3.3Vdc 10%, VSS = 0 Vdc, TA = TL to TH) Characteristic Frequency of operation Crystal option External clock option Internal operating frequency (fOSC/2) Using crystal Using external clock Cycle time (see Figure 9-1) Crystal oscillator start-up time (see Figure 9-1) Stop recovery start-up time (crystal oscillator) RC oscillator stabilization time A/D converter stabilization time External RESET input pulse width Power-on RESET output pulse width 4064 cycle 16 cycle Watchdog RESET output pulse width Watchdog time-out EEPROM byte erase time 0 to 70 (standard) - 40 to 85 (extended) - 40 to 125 (automotive) EEPROM byte program time(1) 0 to 70 (standard) - 40 to 85 (extended) - 40 to 125 (automotive) Timer (see Figure 11-13) Resolution(2) Input capture pulse width Input capture pulse period Interrupt pulse width (edge-triggered) Interrupt pulse period OSC1 pulse width(5) Write/Erase endurance(6)(7) Data retention
(6)(7)
Symbol fOSC fOSC fOP fOP tCYC tOXOV tILCH tADRC tADON tRL tPORL tPORL tDOGL tDOG tERA tERA tERA tPROG tPROG tPROG tRESL tTH, tTL tTLTL tILIH tILIL tOH, tOL -- --
Min -- dc -- dc 1000 --
Max 2.0 2.0 1.0 1.0 -- 100 100 5 500
Unit MHz MHz MHz MHz ns ms ms s s tCYC tCYC tCYC tCYC tCYC ms ms ms ms ms ms tCYC ns tCYC ns tCYC ns cycles years
1.5 4064 16 1.5 6144 30 30 30 30 30 30 4 250 --(3) 250 --(4) 200 10000 10
-- -- -- -- 7168 -- -- -- -- -- -- -- -- -- -- -- --
11
(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when programming the EEPROM. (2) Since a 2-bit prescaler in the timer must count four external cycles (tCYC), this is the limiting factor in determining the timer resolution. (3) The minimum period tTLTL should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 tCYC. (4) The minimum period tILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 tCYC. (5) tOH and tOL should not total less than 500ns. (6) At a temperature of 85C (7) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information.
MC68HC05B6 Rev. 4.1
ELECTRICAL SPECIFICATIONS
Freescale 11-11
tTLTL External signal (TCAP1, TCAP2)
tTH
tTL
Figure 11-13 Timer relationship
11
Freescale 11-12
ELECTRICAL SPECIFICATIONS
MC68HC05B6 Rev. 4.1
12
MECHANICAL DATA
12.1 12.1.1 MC68HC05B family pin configurations 52-pin plastic leaded chip carrier (PLCC)
VRL NC/NU PD5/AN5 PD6/AN6 PD7/AN7 TCMP1 TCMP2 TDO SCLK RDI PC0 PC1 PC2/ECLK
7 6 5 4 3 2 52 51 50 49 48 47
VRH PD4/AN4 VDD PD3/AN3 PD2/AN2 PD1/AN1 PD0/AN0 NC/VPP6 OSC1 OSC2 RESET IRQ PLMA
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
46 45 44 43 42 41 40 39 38 37 36 35 34
PC3 PC4 PC5 PC6 PC7 VSS VPP1/NU PB0 PB1 PB2 PB3 PB4 PB5
Device MC68HC05B4 MC68HC05B6 MC68HC05B8 MC68HC05B16 MC68HC05B32 MC68HC705B5 MC68HC705B16 MC68HC705B16N MC68HC705B32
Pin 6 NC NC NC NC NC NC NU NU NU
Pin 15 NC NC NC NC NC VPP6 VPP6 VPP6 VPP6
Pin 40 NU VPP1 VPP1 VPP1 VPP1 NU VPP1 VPP1 VPP1
NC = Not connected NU = Non-user pin (Should be tied to VSS in an electrically noisy environment)
PLMB TCAP1 TCAP2 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6
12
Figure 12-1 52-pin PLCC pinout for the MC68HC05B6
TPG
MC68HC05B6 Rev. 4.1
MECHANICAL DATA
Freescale 12-1
12.1.2
64-pin quad flat pack (QFP)
PC2/ECLK PC3 PC4 PC5 PC6 PC7 VSS VPP1/NC NC NC/NU PB0 PB1 PB2 PB3 PB4 PB5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
PC1 PC0 NC NC NC NC NC RDI SCLK TDO TCMP2 TCMP1 PD7/AN7 PD6/AN6 PD5/AN5 NC
PB6 PB7 NC NC PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 NC TCAP2 TCAP1 PLMB D/A
MC68HC05B4 MC68HC05B6 MC68HC05B8 MC68HC05B16 MC68HC05B32 MC68HC705B5 MC68HC705B16 MC68HC705B16N MC68HC705B32
12
NC = Not connected NU = Non-user pin (Should be tied to VSS in an electrically noisy environment)
Figure 12-2 64-pin QFP pinout for the MC68HC05B6
VRL VRH PD4/AN4 VDD PD3/AN3 PD2/AN2 PD1/AN1 PD0/AN0 NC NC NC/VPP6 OSC1 OSC2 RESET IRQ PLMA D/A
Device
Pin 27 NC NC
Pin 55 NC NC
Pin 57 NC VPP1
Not available in this package VPP6 VPP6 VPP6 NU NU NC VPP1 VPP1 VPP1
TPG
Freescale 12-2
MECHANICAL DATA
MC68HC05B6 Rev. 4.1
12.1.3
56-pin shrink dual in line package (SDIP)
TCMP1 PD7 PD6 PD5 NC NC/NU NC VRL VRH PD4 VDD PD3 PD2 PD1 PD0 NC/VPP6 OSC1 OSC2 RESET IRQ PLMA PLMB TCAP1 TCAP2 PA7 PA6 PA5 PA4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
TCMP2 TDO SCLK RDI PC0 PC1 NC PC2 PC3 PC4 PC5 PC6 PC7 VSS VPP1/NC PB0 PB1 PB2 PB3 PB4 PB5 NC PB6 PB7 PA0 PA1 PA2 PA3
Device MC68HC05B4 MC68HC05B6 MC68HC05B8 MC68HC05B16 MC68HC05B32 MC68HC705B5 MC68HC705B16 MC68HC705B16N MC68HC705B32 NC = Not connected
Pin 6 NC NC NC NC NC NC
Pin 16 NC NC NC NC NC VPP6 Contact Sales
Pin 42 NC VPP1 VPP1 VPP1 VPP1 NC
Not available in this package NU VPP6 VPP1
NU = Non-user pin (Should be tied to VSS in an electrically noisy environment)
12
Figure 12-3 56-pin SDIP pinout for the MC68HC05B6
TPG
MC68HC05B6 Rev. 4.1
MECHANICAL DATA
Freescale 12-3
12.2 12.2.1
MC68HC05B6 mechanical dimensions 52-pin plastic leaded chip carrier (PLCC)
0.18 M T N S -P S L S -M S Y BRK B
-N-
-L-
Case No. 778-02 52 Lead PLCC w/o pedestal
W
-M-
G1
Z1
pin 52
-P-
pin 1 V A R
X U 0.18 M T N S -P S 0.18 M T L S -M S 0.18 M T L S -M S L S -M S N S -P S N S -P S
Z C G G1 0.25 S T L S -M S
0.10 JE N S -P S
-T- SEATING PLANE
Dim. A B C
Min. 19.94 19.94 4.20 2.29 0.33 0.66 0.51 0.64 19.05
Max. 20.19 20.19 4.57 2.79 0.48 0.81 -- -- 19.20
Notes
Dim. U V
Min. 19.05 1.07 1.07 1.07 -- 2 18.04 1.02 2
Max. 19.20 1.21 1.21 1.42 0.50 10 18.54 -- 10
12
E F G H J K R
1.27 BSC
1. Datums -L-, -M-, -N- and -P- are determined where top of lead shoulder exits plastic body at mould parting line. 2. Dimension G1, true position to be measured at datum -T- (seating plane). 3. Dimensions R and U do not include mould protrusion. Allowable mould protrusion is 0.25mm per side. 4. Dimensions and tolerancing per ANSI Y 14.5M, 1982. 5. All dimensions in mm.
W X Y Z G1 K1 Z1
Figure 12-4 52-pin PLCC mechanical dimensions
TPG
Freescale 12-4
MECHANICAL DATA
MC68HC05B6 Rev. 4.1
12.2.2
64-pin quad flat pack (QFP)
L
48 49 33 0.20 M C A - B S D S 0.20 M H A - B S D S 32
B B P - A, B, D Detail "A" F
Detail "A" 64 1 -DA 0.20 M C A - B S D S 0.05 A - B S 0.20 M H A - B S D S 16 17
0.05 A - B
L
-A-
Case No. 840C 64 lead QFP
-BB
V
J
N Base Metal
D Section B-B 0.20 M C A - B S D S
U
Detail "C" M
T R Q
E C -CSeating Plane H G
Datum -H- Plane M
K W X
Dim. A B C D E F G H J K L
Min. 13.90 13.90 2.067 0.30 2.00 0.30 0.067 0.130 0.50
Max. 14.10 14.10 2.457 0.45 2.40 -- 0.250 0.230 0.66
Notes
1. Datum Plane -H- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 2. Datums A-B and -D to be determined at Datum Plane -H-. 3. Dimensions S and V to be determined at seating plane -C-. 4. Dimensions A and B do not include mould protrusion. Allowable mould protrusion is 0.25mm per side. Dimensions A and B do include mould mismatch and are determined at Datum Plane -H-. 5. Dimension D does not include dambar protrusion. Allowable dambar protrusion shall be 0.08 total in excess of the D dimension at maximum material condition. Dambar cannot be located on the lower radius or the foot. 6. Dimensions and tolerancing per ANSI Y 14.5M, 1982. 7. All dimensions in mm.
Dim. M N P Q R S T U V W X
Min. 5 0.130 2 0.13 16.20 9 16.20 1.10
Max. 10 0.170 8 0.30 16.60 15 16.60 1.30
0.40 BSC
0.80 BSC
0.20 REF
12
0.042 NOM
12.00 REF
Figure 12-5 64-pin QFP mechanical dimensions
TPG
MC68HC05B6 Rev. 4.1
MECHANICAL DATA
Freescale 12-5
12.2.3
56-pin shrink dual in line package (SDIP)
-A56 29 -B28 M J C H L
Case No. 859-01 56 lead SDIP
1
0.25 M T B S
-TSeating Plane D
K G F E
N
0.25 M T A S
Dim. A B C D E F G
Min. 51.69 13.72 3.94 0.36 0.81
Max. 52.45 14.22 5.08 0.56 1.17
Notes
1. Due to space limitations, this case shall be represented by a general case outline, rather than one showing all the leads. 2. Dimensions and tolerancing per ANSI Y 14.5 1982. 3. All dimensions in mm. 4. Dimension L to centre of lead when formed parallel. 5. Dimensions A and B do not include mould flash. Allowable mould flash is 0.25 mm.
Dim. H J K L M N
Min. 0.20 2.92 0 0.51
Max. 0.38 3.43 15 1.02
7.62 BSC
15.24 BSC
0.89 BSC 1.778 BSC
Figure 12-6 56-pin SDIP mechanical dimensions
12
TPG
Freescale 12-6
MECHANICAL DATA
MC68HC05B6 Rev. 4.1
13
ORDERING INFORMATION
This section describes the information needed to order the MC68HC05B6 and other family members. To initiate a ROM pattern for the MCU, it is necessary to contact your local field service office, local sales person or Freescale representative. Please note that you will need to supply details such as: mask option selections; temperature range; oscillator frequency; package type; electrical test requirements; and device marking details so that an order can be processed, and a customer specific part number allocated. Refer to Table 13-1 for appropriate part numbers. The part number consists of the device title plus the appropriate suffix. For example, the MC68HC05B6 in 52-pin PLCC package at -40 to +85C would be ordered as: MC68HC05B6CFN. Table 13-1 MC order numbers
Device Title MC68HC05B6 Package Type 52-pin PLCC 64-pin QFP 56-pin SDIP 52-pin PLCC 64-pin QFP 56-pin SDIP 52-pin PLCC 64-pin QFP 56-pin SDIP 52-pin PLCC 64-pin QFP 56-pin SDIP 52-pin PLCC 64-pin QFP 56-pin SDIP 52-pin PLCC 56-pin SDIP 52-pin PLCC 64-pin QFP 52-pin PLCC 64-pin QFP 56-pin SDIP 52-pin PLCC 64-pin QFP 56-pin SDIP Suffix 0 to 70C FN FU B FN FU B FN FU B FN FU B FN FU B FN B FN FU FN FU FN FU B Suffix Suffix -40 to +85C -40 to +105C CFN VFN CFU VFU CB VB CFN VFN CFU VFU CB VB CFN VFN CFU VFU CB VB CFN VFN CFU VFU CB VB CFN N/A CFU N/A Contact Sales N/A CFN VFN CB VB CFN VFN CFU VFU CFN VFN CFU VFU Contact Sales CFN N/A CFU N/A CB N/A Suffix -40 to +125C MFN MFU MB MFN MFU MB MFN MFU MB MFN MFU MB N/A N/A N/A MFN MB MFN MFU MFN MFU N/A N/A N/A
MC68HC05B4
MC68HC05B8
MC68HC05B16
MC68HC05B32 MC68HC705B5 MC68HC705B16 MC68HC705B16N
13
MC68HC705B32
MC68HC05B6 Rev. 4.1
ORDERING INFORMATION
Freescale 13-1
13.1
EPROMS
For the MC68HC05B6, an 8 kbyte EPROM programmed with the customer's software (positive logic for address and data) should be submitted for pattern generation. All unused bytes should be programmed to $00. The size of EPROM which should be used for all other family members is listed in Table 13-2. The EPROM should be clearly labelled, placed in a conductive IC carrier and securely packed.
Table 13-2 EPROMs for pattern generation
Device MC68HC05B4 MC68HC05B8 MC68HC05B16 MC68HC05B32 Size of EPROM 8 kbyte 8 kbyte 16 kbyte 32 kbyte
13.2
Verification media
All original pattern media (EPROMs) are filed for contractual purposes and are not returned. A computer listing of the ROM code will be generated and returned with a listing verification form. The listing should be thoroughly checked and the verification form completed, signed and returned to Freescale. The signed verification form constitutes the contractual agreement for creation of the custom mask. If desired, Freescale will program blank EPROMs (supplied by the customer) from the data file used to create the custom mask, to aid in the verification process.
13.3
ROM verification units (RVU)
Ten MCUs containing the customer's ROM pattern will be provided for program verification. These units will have been made using the custom mask but are for ROM verification only. For expediency, they are usually unmarked and are tested only at room temperature (25C) and at 5 Volts. These RVUs are included in the mask charge and are not production parts. They are neither backed nor guaranteed by Freescale Quality Assurance.
13
Freescale 13-2
ORDERING INFORMATION
MC68HC05B6 Rev. 4.1
A
MC68HC05B4
The MC68HC05B4 is a device similar to the MC68HC05B6, but without EEPROM and having a reduced ROM size of 4 kbytes. The entire MC68HC05B6 data sheet applies to the MC68HC05B4, with the exceptions outlined in this appendix.
A.1
* * *
Features
4158 bytes User ROM (including 14 bytes User vectors) No EEPROM High speed version not available
Section 3.5, `EEPROM', therefore, does not apply to the MC68HC05B4, and the register at address $07 only allows the user to select whether or not the ECLK should appear at PC2, using bit 3 of $07. All other bits of this register read as `0'.
Table A-1 Mode of operation selection
IRQ pin VSS to VDD 2VDD 2VDD 2VDD TCAP1 pin VSS to VDD VDD VDD VDD PD3 X 0 1 1 PD4 X X 0 1 Mode Single chip Self check Serial RAM loader Jump to any address
14
MC68HC05B6 Rev. 4.1 MC68HC05B4 Freescale A-1
RESET IRQ OSC2 OSC1
COP watchdog 4158 bytes User ROM (including 14 bytes User vectors) Port A
Oscillator
/ 2 / /32
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2/ECLK PC3 PC4 PC5 PC6 PC7 TCMP1 TCMP2 TCAP1 TCAP2 RDI SCLK TDO
M68HC05 CPU
VDD VSS
432 bytes self check ROM
PD0/AN0 PD1/AN1 PD2/AN2 PD3/AN3 PD4/AN4 PD5/AN5 PD6/AN6 PD7/AN7 VRH VRL PLMA D/A PLMB D/A
Port D
8-bit A/D converter
176 bytes RAM 16-bit programmable timer
PLM
SCI
Figure A-1 MC68HC05B4 block diagram
14
Freescale A-2 MC68HC05B4 MC68HC05B6 Rev. 4.1
Port C
Port B
MC68HC05B4 $0000 I/O (32 bytes) $0020 Page 0 User ROM (48 bytes)
Registers
Port A data register Port B data register Port C data register Port D input data register Port A data direction register Port B data direction register Port C data direction register EEPROM/ECLK control register $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F
$0050 RAM (176 bytes) Stack
A/D data register A/D status/control register Pulse length modulation A Pulse length modulation B Miscellaneous register SCI baud rate register SCI control register 1 SCI control register 2 SCI status register SCI data register
$00C0 $0100
$0200
Self-check ROM I (192 bytes)
Timer control register Timer status register Capture high register 1 Capture low register 1 Compare high register 1
$02C0 $0F00 User ROM (4096 bytes) Self-check ROM II (240 bytes)
Compare low register 1 Counter high register Counter low register Alternate counter high register Alternate counter low register Capture high register 2 Capture low register 2 Compare high register 2 Compare low register 2
$1F00
$1FF0 $1FF2-3 SCI $1FF4-5 Timer overflow $1FF6-7 Timer output compare 1& 2 $1FF8-9 Timer input capture 1 & 2 $1FFA-B External IRQ $1FFC-D SWI $1FFE-F Reset/power-on reset
User vectors (14 bytes) Reserved
Figure A-2 Memory map of the MC68HC05B4
14
MC68HC05B6 Rev. 4.1 MC68HC05B4 Freescale A-3
Table A-2 Register outline
State on reset Undefined Undefined PC2/ ECLK PD7/ AN7 PD6/ AN6 PD5/ AN5 PD4/ AN4 PD3/ AN3 PD2/ AN2 PD1/ AN1 PD0/ AN0 Undefined Undefined 0000 0000 0000 0000 0000 0000 0 0 0 0 0 ECLK CH3 0 CH2 0 CH1 0 CH0 0000 0000 0000 0000 COCO ADRC ADON 0000 0000 0000 0000 0000 0000 INTN SCT1 RIE RDRF INTE SCT0 M ILIE IDLE SFA SCT0 TE OR SFB SCR2 RE NF SM SCR1 RWU FE WDOG ?001 000?
(2)
Register name Port A data (PORTA) Port B data (PORTB) Port C data (PORTC) Port D data (PORTD) Port A data direction (DDRA) Port B data direction (DDRB) Port C data direction (DDRC) ECLK control A/D data (ADDATA) A/D status/control (ADSTAT) Pulse length modulation A (PLMA) Pulse length modulation B (PLMB) Miscellaneous SCI baud rate (BAUD) SCI control 1 (SCCR1) SCI control 2 (SCCR2) SCI status (SCSR) SCI data (SCDR) Timer control (TCR) Timer status (TSR) Input capture high 1 Input capture low 1 Output compare high 1 Output compare low 1 Timer counter high Timer counter low Alternate counter high Alternate counter low Input capture high 2 Input capture low 2 Output compare high 2 Output compare low 2
Address bit 7 $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
$000C POR(1) INTP $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F ICIE ICF1 OCIE OCF1 SPC1 R8 TIE TDRE SPC0 T8 TCIE TC
SCR0 00uu uuuu LBCL uuuu uuuu SBK 0000 0000 1100 000u 0000 0000
WAKE CPOL CPHA
TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0 TOF ICF2 OCF2 uuuu uuuu Undefined Undefined Undefined Undefined 1111 1111 1111 1100 1111 1111 1111 1100 Undefined Undefined Undefined Undefined
(1) This bit is set each time there is a power-on reset. (2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1=watchdog enabled, 0=watchdog disabled.
14
Freescale A-4 MC68HC05B4 MC68HC05B6 Rev. 4.1
A.2
Self-check mode
The self-check function available on the MC68HC05B4 provides an internal capability to determine if the device is functional. Self-check is performed using the circuit shown in Figure A-3. Port C pins PC0-PC3 are monitored for the self-check results (light emitting diodes are shown but other devices could be used), and are interpreted as described in Table A-3. The self-check mode is entered by applying 2 x VDD dc (via a 4.7k resistor) to the IRQ pin and 5V dc input (via a 4.7k resistor) to the TCAP1 pin and then depressing the reset switch to execute a reset. After reset, the following tests are performed automatically and once completed they continually repeat. A good device will exhibit flashing LEDs; a bad device will be indicated by the LEDs holding at one value. Note: I/0 RAM ROM Timer SCI A/D PLM Self-check code can be obtained from your local Freescale representative. -- -- -- -- -- -- -- Functionally exercises ports A, B, C and D Counter test for each RAM byte Exclusive OR with odd ones parity result Tracks counter registers and checks ICF1, ICF2, OCF1, OCF2 and TOF flags Transmission test; check for RDRF, TDRE, TC and FE flags Check A/D functionality on internal channels: VRL, VRH and (VRL + VRH)/2 Checks the PLM basic functionality Tests external timer and SCI interrupts Tests the watchdog
Interrupts -- Watchdog--
Caution: This document includes descriptions of the various self-check and bootstrap mechanisms that are currently implemented as firmware in the non-user ROM areas of the MC68HC05B6 and related devices. As these firmware routines are intended primarily to help Freescale's engineers test the devices, they may be changed or removed at any time. For this reason, Freescale recommends the self-check and bootstrap routines are not called from the user software. Customers who do call these routines from the user software do so at their own risk.
14
MC68HC05B6 Rev. 4.1 MC68HC05B4 Freescale A-5
Table A-3 MC68HC05B4 self-check results
PC3 1 0 1 1 1 1 1 0 0 0 PC2 0 1 0 0 1 1 1 0 0 0 Flashing All others PC1 0 1 1 1 0 0 1 0 1 1 PC0 1 0 0 1 0 1 0 1 0 1 Bad port Bad port Bad RAM Bad ROM Bad Timer Bad SCI Bad A/D Bad PLM Bad interrupts Bad watchdog Good device Bad device, bad port etc. Remarks
`0' indicates LED on; `1' indicates LED off
14
Freescale A-6 MC68HC05B4 MC68HC05B6 Rev. 4.1
P1 10 nF RESET 15 NC 18 RESET 0.01 F 22 pF 4 MHz 22 pF 8 VRH 10 VDD 16 OSC1 17 OSC2 47 F
GND +5V 2xVDD
10 M 4k7
IRQ 6 40 50 52 20 21 2 51 NC VPP1
19 BC239
MC68HC05B4 (52-pin package)
RDI TDO PLMA PLMB TCMP1 SCLK
TCAP2 TCMP2 1
23 4k7
EEPROM tested
TCAP1 22 32 PB7 33 PB6 34 PB5 35 PB4 36 PB3 37 PB2 38 PB1 39 PB0
4k7
EEPROM not tested
4k7
3 4 5 9 11 12 13 14 24 25 26 27 28 29 30 31
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
PC7 PC6 PC5 PC4 PC3 PC2 PC1 VSS VRL 41 7 PC0
42 43 44 45 46 47 48 49 680 680 680 680
Note:
For the MC68HC05B4, switches on PB5 and PB6 have no effect All resistors are 10 k, unless otherwise stated.
Figure A-3 MC68HC05B4 self-check schematic diagram
14
MC68HC05B6 Rev. 4.1 MC68HC05B4 Freescale A-7
THIS PAGE LEFT BLANK INTENTIONALLY
14
Freescale A-8 MC68HC05B4 MC68HC05B6 Rev. 4.1
B
MC68HC05B8
The MC68HC05B8 is a device similar to the MC68HC05B6, but with an increased ROM size of 7.25 kbytes. The entire MC68HC05B6 data sheet applies to the MC68HC05B8, with the exceptions outlined in this appendix.
B.1
* *
Features
7230 bytes User ROM (including 14 bytes User vectors) High speed version available
14
TPG
MC68HC05B6 Rev. 4.1
MC68HC05B8
Freescale B-1
VPP1
Charge pump
7230 bytes User ROM (including 14 bytes User vectors)
Port A
256 bytes EEPROM
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2/ECLK PC3 PC4 PC5 PC6 PC7 TCMP1 TCMP2 TCAP1 TCAP2 RDI SCLK TDO PLMA D/A PLMB D/A
RESET IRQ OSC2 OSC1
COP watchdog Port B 432 bytes self check ROM 176 bytes RAM 16-bit programmable timer Port D 8-bit A/D converter SCI PLM Port C
Oscillator
/ 2 / /32
M68HC05 CPU
VDD VSS
PD0/AN0 PD1/AN1 PD2/AN2 PD3/AN3 PD4/AN4 PD5/AN5 PD6/AN6 PD7/AN7 VRH VRL
Figure B-1 MC68HC05B8 block diagram
14
TPG
Freescale B-2
MC68HC05B8
MC68HC05B6 Rev. 4.1
MC68HC05B8 $0000 I/O (32 bytes) $0020 Page 0 User ROM (48 bytes)
Registers
Port A data register Port B data register Port C data register Port D input data register Port A data direction register Port B data direction register Port C data direction register EEPROM/ECLK control register $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F
$0050 RAM (176 bytes) Stack OPTR (1 byte) Non protected (31 bytes) EEPROM (256 bytes) Protected (224 bytes) $0200 Self-check ROM I (192 bytes)
A/D data register A/D status/control register Pulse length modulation A Pulse length modulation B Miscellaneous register SCI baud rate register SCI control register 1 SCI control register 2 SCI status register SCI data register Timer control register Timer status register Capture high register 1 Capture low register 1 Compare high register 1
$00C0 $0100 $0101 $0120
$02C0 $0300 User ROM (7168 bytes) Self-check ROM II (240 bytes)
Compare low register 1 Counter high register Counter low register Alternate counter high register Alternate counter low register Capture high register 2 Capture low register 2 Compare high register 2 Compare low register 2
$1F00
$1FF0 $1FF2-3 SCI Timer overflow $1FF4-5 $1FF6-7 Timer output compare 1& 2 $1FF8-9 Timer input capture 1 & 2 External IRQ $1FFA-B $1FFC-D SWI $1FFE-F Reset/power-on reset
User vectors (14 bytes)
Options register $0100
Reserved
Figure B-2 Memory map of the MC68HC05B8
14
TPG
MC68HC05B6 Rev. 4.1
MC68HC05B8
Freescale B-3
Table B-1 Register outline
State on reset Undefined Undefined PC2/ ECLK PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undefined Undefined 0000 0000 0000 0000 0000 0000 0 0 0 0 0 ECLK E1ERA E1LAT E1PGM 0000 0000 0000 0000 COCO ADRC ADON CH3 CH2 CH1 CH0 0000 0000 0000 0000 0000 0000 INTN SCT1 RIE RDRF INTE SCT0 M ILIE IDLE SFA SCT0 TE OR SFB SCR2 RE NF SM SCR1 RWU FE WDOG(2) ?001 000? SCR0 00uu uuuu LBCL SBK Undefined 0000 0000 1100 000u 0000 0000 ICIE ICF1 OCIE OCF1 TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0 TOF ICF2 OCF2 Undefined Undefined Undefined Undefined Undefined 1111 1111 1111 1100 1111 1111 1111 1100 Undefined Undefined Undefined Undefined EE1P SEC Not affected SPC1 R8 TIE TDRE SPC0 T8 TCIE TC
Register name Port A data (PORTA) Port B data (PORTB) Port C data (PORTC) Port D data (PORTD) Port A data direction (DDRA) Port B data direction (DDRB) Port C data direction (DDRC) EEPROM/ECLK control A/D data (ADDATA) A/D status/control (ADSTAT) Pulse length modulation A (PLMA) Pulse length modulation B (PLMB) Miscellaneous SCI baud rate (BAUD) SCI control 1 (SCCR1) SCI control 2 (SCCR2) SCI status (SCSR) SCI data (SCDR) Timer control (TCR) Timer status (TSR) Input capture high 1 Input capture low 1 Output compare high 1 Output compare low 1 Timer counter high Timer counter low Alternate counter high Alternate counter low Input capture high 2 Input capture low 2 Output compare high 2 Output compare low 2 Options (OPTR)(3)
Address bit 7 $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
$000C POR(1) INTP $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F $0100
WAKE CPOL CPHA
(1) This bit is set each time there is a power-on reset. (2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1=watchdog enabled, 0=watchdog disabled. (3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.
14
TPG
Freescale B-4
MC68HC05B8
MC68HC05B6 Rev. 4.1
C
MC68HC705B5
The MC68HC705B5 is a device similar to the MC68HC05B6, but with the 6 kbytes ROM and 256 bytes EEPROM replaced by a single EPROM array. In addition, the self-check routines available on the MC68HC05B6 are replaced by bootstrap firmware. The MC68HC705B5 is intended to operate as a one time programmable (OTP) version of the MC68HC05B6 without EEPROM or the MC68HC05B4, meaning that the application program can never be erased once it has been loaded into the EPROM. The entire MC68HC05B6 data sheet applies to the MC68HC705B5, with the exceptions outlined in this appendix.
C.1
* * * * * * * * *
Features
6206 bytes EPROM (including 14 bytes User vectors) No EEPROM Bootstrap firmware Simultaneous programming of up to 4 bytes Data protection for program code Optional pull-down resistors on port B and port C MC68HC05B6 mask options are programmable using control bits held in the options register 52-pin PLCC and 56-pin SDIP packages High speed version not available
14
MC68HC05B6 Rev. 4.1 MC68HC705B5 Freescale C-1
VPP6
6206 bytes EPROM (including 14 bytes User vectors)
496 bytes bootstrap ROM
Port A
256 bytes EPROM1
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2/ECLK PC3 PC4 PC5 PC6 PC7 TCMP1 TCMP2 TCAP1 TCAP2 RDI SCLK TDO PLMA D/A PLMB D/A
RESET IRQ OSC2 OSC1
COP watchdog
Oscillator Port C
/ 2 / /32
M68HC05 CPU
176 bytes RAM
VDD VSS
PD0/AN0 PD1/AN1 PD2/AN2 PD3/AN3 PD4/AN4 PD5/AN5 PD6/AN6 PD7/AN7 VRH VRL
16-bit programmable timer Port D 8-bit A/D converter
SCI
PLM
Figure C-1 MC68HC705B5 block diagram
14
Freescale C-2 MC68HC705B5 MC68HC05B6 Rev. 4.1
Port B
MC68HC705B5 $0000 I/O (32 bytes) $0020 Page 0 User EPROM (48 bytes)
Registers
Port A data register Port B data register Port C data register Port D input data register Port A data direction register Port B data direction register Port C data direction register EPROM/ECLK control register $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F
$0050 RAM (176 bytes) Stack
A/D data register A/D status/control register Pulse length modulation A Pulse length modulation B Miscellaneous register
$00C0 $0100
User EPROM1 (256 bytes) $0200
SCI baud rate register SCI control register 1 SCI control register 2 SCI status register SCI data register Timer control register Timer status register Capture high register 1 Capture low register 1 Compare high register 1 Compare low register 1 Counter high register Counter low register Alternate counter high register Alternate counter low register Capture high register 2 Capture low register 2 Compare high register 2 Compare low register 2
Bootstrap ROMI (256 bytes)
$0300 $0800 User EPROM (5888 bytes) $1EFE $1F00
Options register
Bootstrap ROMII (240 bytes)
$1FF0 $1FF2-3 SCI Timer overflow $1FF2-3 $1FF2-3 Timer output compare 1& 2 $1FF2-3 Timer input capture 1 & 2 External IRQ $1FF2-3 $1FF2-3 SWI $1FF2-3 Reset/power-on reset
User vectors (14 bytes)
Options register $1EFE
Reserved
Figure C-2 Memory map of the MC68HC705B5
14
MC68HC05B6 Rev. 4.1 MC68HC705B5 Freescale C-3
Table C-1 Register outline
Register name Port A data (PORTA) Port B data (PORTB) Port C data (PORTC) Port D data (PORTD) Port A data direction (DDRA) Port B data direction (DDRB) Port C data direction (DDRC) EPROM/ECLK control A/D data (ADDATA) A/D status/control (ADSTAT) Pulse length modulation A (PLMA) Pulse length modulation B (PLMB) Miscellaneous SCI baud rate (BAUD) SCI control 1 (SCCR1) SCI control 2 (SCCR2) SCI status (SCSR) SCI data (SCDR) Timer control (TCR) Timer status (TSR) Input capture high 1 Input capture low 1 Output compare high 1 Output compare low 1 Timer counter high Timer counter low Alternate counter high Alternate counter low Input capture high 2 Input capture low 2 Output compare high 2 Output compare low 2 Options (OPTR)(4) Address bit 7 $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C POR(2) INTP $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F $1EFE EPP 0 ICIE ICF1 OCIE OCF1 TOF ICF2 OCF2 SPC1 R8 TIE TDRE SPC0 T8 TCIE TC RIE RDRF INTN SCT1 INTE SCT0 M ILIE IDLE SFA SCT0 TE OR SFB SCR2 RE NF SM SCR1 RWU FE COCO ADRC ADON 0 CH3 CH2 CH1 CH0 EPPT(1) ELAT EPGM ECLK PD7 PD6 PD5 PD4 PD3 PC2/ ECLK PD2 PD1 PD0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Undefined Undefined Undefined Undefined 0000 0000 0000 0000 0000 0000 u?00 0uuu 0000 0000 0000 0000 0000 0000 0000 0000 WDOG(3) ?001 000? SCR0 00uu uuuu LBCL SBK uuuu 0000 0000 1100 000u 0000 0000 TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0 uuuu Undefined Undefined Undefined Undefined 1111 1111 1111 1100 1111 1111 1111 1100 Undefined Undefined Undefined Undefined RTIM RWAT WWAT PBPD PCPD Not affected
WAKE CPOL CPHA
(1) This bit reflects the state of the EPP bit in the options register ($1EFE) at reset. (2) This bit is set each time the device is powered-on. (3) The state of the WDOG bit after reset depends on the mask option selected; `1' = watchdog enabled and `0' = watchdog disabled. (4) Because this register is implemented in EPROM, reset has no effect on the state of the individual bits.
14
Freescale C-4 MC68HC705B5 MC68HC05B6 Rev. 4.1
C.2
EPROM
The MC68HC705B5 has a total of 6206 bytes of EPROM, 256 bytes being reserved for the EPROM1 array (see Figure C-2). The EPP bit (EPROM protect) is not operative on the EPROM1 array, making it possible to program it after the main EPROM has been programmed and protected. The reset and interrupt vectors are located at $1FF2-$1FFF and the EPROM control register described in Section C.3.1 is located at address $0007. The EPROM array is supplied by the VPP6 pin in both read and programming modes. Typically the user's software will be loaded in a programming board where VPP6 is controlled by one of the bootstrap loader routines (bootloader mode). It will then be placed in an application where no programming occurs (user mode). In this case the VPP6 pin should be hardwired to VDD. An erased EPROM byte reads as $00. Warning: A minimum VDD voltage must be applied to the VPP6 pin at all times, including power-on, as a lower voltage could damage the device. Unless otherwise stated, EPROM programming is guaranteed at ambient (25C) temperature only
C.2.1
EPROM programming operation
The User program can be used to program some EPROM locations, provided the proper procedure is followed. In particular, the programming sequence must be running in RAM, as the EPROM will not be available for code execution while the ELAT bit is set. The VPP6 switching must occur externally, after the EPGM bit is set, for example, under the control of a signal generated on a pin by the programming routine. Note: Unless the part has a window for reprogramming, only the cumulative programming of bits to logic 1 is possible if multiple programming is made on the same byte.
To allow simultaneous programming of up to 4 bytes, they must be in the same group of addresses which share the same most significant address bits; only the two LSBs can change.
14
MC68HC05B6 Rev. 4.1 MC68HC705B5 Freescale C-5
C.3 C.3.1
EPROM registers EPROM control register
Address EPROM/ECLK control $0007 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset u?00 0uuu
EPPT(1) ELAT EPGM ECLK
(1) This bit is a copy of the EPP bit in the options register at $1EFE and therefore its state on reset will be the same as that for the EPP bit.
Bit 7 -- Factory use only This bit is strictly for factory use only and will always read zero. EPPT -- EPROM protect test bit This bit is a copy of the EPROM protect bit (EPP) located in the option register. When ELAT is set, the EPPT bit can be tested by the software to check if the EPROM array is protected or not, since the EPROM content is not available when ELAT is set. POR or external reset modifies this bit to reflect the state of the EPP bit in the options register. ELAT -- EPROM programming latch enable bit 1 (set) - When set, this bit allows latching of the address and up to 4 data bytes for further programming, provided EPGM is zero. When cleared, program and interrupt routines can be executed and data can be read in the EPROM or firmware ROM.
0 (clear) -
STOP, power-on and external reset clear this bit. EPGM -- EPROM programming bit This bit is the EPROM program enable bit. It can be set to `1' to enable programming only after ELAT is set and at least one byte is written to the EPROM. It is not possible to clear EPGM by software, but clearing ELAT will always clear EPGM. ECLK -- External clock option bit See Section 4.3.
14
Freescale C-6 MC68HC705B5 MC68HC05B6 Rev. 4.1
C.4
Options register (OPTR)
Address Options (OPTR)(1) $1EFE bit 7 bit 6 EPP bit 5 0 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset
RTIM RWAT WWAT PBPD PCPD Not affected
(1) This register is implemented in EPROM, therefore reset has no effect on the state of the individual bits.
Note:
This register can only be written to while the device is in bootloader mode.
Bit 7 -- Factory use only Warning: This bit is strictly for factory use only and will always read zero to avoid accidental damage to the device. Any attempt to write to this bit could result in physical damage. EPP -- EPROM protect This bit protects the contents of the main EPROM against accidental modification; it has no effect on reading or executing code in the EPROM. 1 (set) - EPROM contents are protected. EPROM contents are not protected.
0 (clear) - RTIM -- Reset time
This bit can modify tPORL, i.e. the time that the RESET pin is kept low following a power-on reset. This feature is handled in the ROM part via a mask option. 1 (set) - tPORL = 16 cycles. tPORL = 4064 cycles.
0 (clear) -
RWAT -- Watchdog after reset This bit can modify the status of the watchdog counter after reset. 1 (set) - The watchdog will be active immediately following power-on or external reset (except in bootstrap mode). The watchdog system will be disabled after power-on or external reset.
0 (clear) -
WWAT -- Watchdog during WAIT mode This bit can modify the status of the watchdog counter during WAIT mode.
14
Freescale C-7
MC68HC05B6 Rev. 4.1
MC68HC705B5
1 (set)
-
The watchdog will be active during WAIT mode. The watchdog system will be disabled during WAIT mode.
0 (clear) -
PBPD - Port B pull-down resistors 1 (set) - Pull-down resistors are connected to all 8 pins of port B; the pull-down, RPD, is active only while the pin is an input. No pull-down resistors are connected.
0 (clear) -
PCPD -- Port C pull-down resistors 1 (set) - Pull-down resistors are connected to all 8 pins of port C; the pull-down, RPD, is active only while the pin is an input. No pull-down resistors are connected.
0 (clear) -
The combination of bit 0 and bit 1 allows the option of pull-down resistors on 0, 8 or 16 inputs. This feature is not available on the MC68HC05B6.
C.5
Bootstrap mode
The 432 bytes of self-check firmware on the MC68HC05B6 are replaced with 496 bytes of bootstrap firmware. The bootstrap firmware located from $0200 to $02FF and $1F00 to $1FEF can be used to program the EPROM, to check if the EPROM is erased and to load and execute data in RAM. When the MC68HC705B5 is placed in the bootstrap mode, the bootstrap reset vector is fetched and the bootstrap firmware starts to execute. Table C-2 shows the conditions required to enter each level of bootstrap mode on the rising edge of RESET. The hold time on the IRQ and TCAP1 pins after the external RESET pin is brought high is two clock cycles.
Table C-2 Mode of operation selection
IRQ pin VSS to VDD + 9 Volts + 9 Volts + 9 Volts + 9 Volts x = Don't care TCAP1 pin VSS to VDD VDD VDD VDD VDD PD2 x 0 x x x PD3 x 1 0 1 0 PD4 x 0 0 1 1 Single chip Erased EPROM verification EPROM parallel bootstrap load EPROM (RAM) serial bootstrap load and execute RAM parallel bootstrap load and execute Mode
14
Freescale C-8 MC68HC705B5 MC68HC05B6 Rev. 4.1
The bootstrap program first copies part of itself into RAM, as the program cannot be executed in ROM during verification/programming of the EPROM. It then sets the TCMP1 output to a logic high level.
Reset
IRQ at 9V? Y TCAP1 set? Y
N
User mode
N
Non-user mode
Bootstrap mode
A
Y
PD4 set? N PD3 set? Y PD2 set? Y N EPROM erased? Y N Red LED on EPROM not erased
Parallel EPROM bootstrap
Program EPROM; parallel load; green LED flashes
N
Non-user mode
Green LED on
Programming OK?
Y
N Red LED on Bad EPROM programming Green LED on EPROM verified
Figure C-3 Modes of operation flow chart (1 of 2)
14
MC68HC05B6 Rev. 4.1 MC68HC705B5 Freescale C-9
A
Bootstrap RAM
N
PD3 set? Y
Serial EPROM (RAM) bootstrap
PD4 set? Y Load next RAM byte
N
Red LED off
Transmit last four programmed locations
N
RAM full? Y Execute RAM program at $0050
Receive address
Receive four data
Bad EPROM programming
Green LED on
Y
Negative address? N
Red LED on
Execute RAM program at $0083
N Program EPROM data at address; green LED flashes Y
Programming OK?
Figure C-4 Modes of operation flow chart (2 of 2)
14
Freescale C-10 MC68HC705B5 MC68HC05B6 Rev. 4.1
C.5.1
Erased EPROM verification
The flowchart in Figure C-3 and Figure C-4 shows that the on-chip bootstrap routines can be used to check if the EPROM is erased (all $00s). If a non $00 byte is detected, the red LED stays on and the routine will stay in a loop. Only when the whole EPROM content is verified as erased will the green LED be turned on.
C.5.2
EPROM parallel bootstrap load
When this mode is selected, the EPROM is loaded in increasing address order with non EPROM segments being skipped by the loader. Simultaneous programming is performed by reading four bytes of data before actual programming is performed, thus dividing the loading time of the internal EPROM by four. When PD2=0, the programming time is set to 5 milliseconds and the program/verify routine takes approximately 15 seconds. Parallel data is entered through Port A, while the 13-bit address is output on port B and PC0 to PC4. If the data comes from an external EPROM, the handshake can be disabled by connecting together PC5 and PC6. If the data is supplied via a parallel interface, handshaking will be provided by PC5 and PC6 according to the timing diagram of Figure C-5. During programming, the green LED flashes at about 3 Hz. Upon completion of the programming operation, the EPROM content is checked against the external data source. If programming is verified the green LED stays on, while an error causes the red LED to be turned on. Figure C-6 shows a circuit that can be used to program the EPROM (or to load and execute data in the RAM). Note: The entire EPROM can be loaded from the external source; if it is desired to leave a segment undisturbed, the data for this segment should be all zeros.
Address
HDSK out (PC5) DATA
HDSK in (PC6) F29
Data read
Data read
Figure C-5 Timing diagram with handshake
14
Freescale C-11
MC68HC05B6 Rev. 4.1
MC68HC705B5
RESET 100k 1N914 1k
RUN
1N914
100F
+
P1 1 2 3
GND +5V VPP
1.0F +
TCAP1 VRH VDD IRQ RESET OSC1
10M 47F +
OSC2 RDI VRL TCAP2 PD7 PD6 PD5 PD3 PD2 PD1 PD0
4.0 MHz 22pF 22pF
red LED 0.01F 470 470 green LED red LED -- programming failed green LED -- programming OK
NC TCMP1 TCMP2 PLMA PLMB
MC68HC705B5
+5V PD4 1 26 27 28 10 9 8 7 6 5 4 3 11 12 13 15 16 17 18 19 TDO SCLK PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 VSS
EPROM 10 k RAM 1N5819 1 k BC309C
VPP NC PGM VCC A0 A1 A2 A3 A4 A5 A6 A7
VPP6
12 k 4k7
PC7
4k7
BC239C
1nF
+
20
CE
27C64
25 24 21 23 2
A8 A9 A10 A11 A12 GND 14
D0 D1 D2 D3 D4 D5 D6 D7
+5V
100 k HDSK out Short circuit if handshake not used
PC5 PC6 PC4 PC3 PC2 PC1 PC0 A12 A11 A10 A9 A8
HDSK in
OE 22
Note:
This circuit is recommended for programming only at 25C and not for use in the end application, or at temperatures other than 25C. If used in the end application, VPP6 should be tied to VDD to avoid damaging the device.
14
Figure C-6 EPROM(RAM) parallel bootstrap schematic diagram Freescale C-12 MC68HC705B5 MC68HC05B6 Rev. 4.1
C.5.3
EPROM (RAM) serial bootstrap load and execute
The serial routine communicates through the SCI with an external host, typically a PC, by means of an RS232 link at 9600 baud, 8-bit, no parity and full duplex. Data format is not ASCII, but 8-bit binary, so a complementary program must be run by the host to supply the required format. Such a program is available for the IBM PC from Freescale. The EPROM bootstrap routines are used to customise the OTP EPROM. To increase the speed of programming, four bytes are programmed in parallel while the data is simultaneously transmitted and received in full duplex. This implies that while 4 bytes are being programmed, the next 4 bytes are received and the preceding 4 bytes are echoed. The format accepted by the serial loader is as follows: [address n high] [address n low] [data(n)] [data (n+1)] [data (n+2)] [data (n+3)] Address n must have the two LSBs at zero so that n, n+1, n+2 and n+3 have identical MSBs. These blocks of four bytes do not need to be contiguous, as a new address is transmitted for each new group. The protocol is as follows: 1 The MC68HC705B5 sends the last two bytes programmed to the host as a prompt; this allows verification by the host of proper programming.
1) In response to the first byte prompt, the host sends the first address byte. 2) After receiving the first address byte, the MC68HC705B5 sends the next byte programmed. 3) The exchange of data continues until the MC68HC705B5 has sent the four data bytes and the host has sent the 2 address data bytes and 4 data bytes. 4) If the data is non zero, it is programmed at the address provided, while the next address and bytes are received and the previous data is echoed. 5) Loop to 1. After reset, the MC68HC705B5 serial bootstrap routine will first echo two blocks of four bytes at $0000, as no data is programmed yet. If the data sent in is $00, no programming in the EPROM takes place, and the contents of the accessed location are returned as a prompt. The entire EPROM memory can be read in this fashion (serial dump). The red LED will be on if the data read from the EPROM is not $00. Serial RAM loading and execute can be accomplished in this mode. A RAM byte will be written if the address sent by the host in the serial protocol points to the RAM. In the RAM bootloader mode, all interrupt vectors are mapped to pseudo-vectors in RAM (see Table C-3). This allows programmers to use their own service-routine addresses. Each pseudo-vector is allowed three bytes of space rather than the two bytes for normal vectors, because an explicit jump (JMP) opcode is needed to cause the desired jump to the user's service-routine address.
14
MC68HC05B6 Rev. 4.1
MC68HC705B5
Freescale C-13
Table C-3 Bootstrap vector targets in RAM
Vector targets in RAM SCI interrupt Timer overflow Timer output compare Timer input capture IRQ SWI $00E4 $00E7 $00EA $00ED $00F0 $00F3
A 10-byte stack is also reserved at the top of the RAM allowing, for example, one interrupt and two sub-routine levels. Program execution is triggered by sending a negative (bit 7 set) high address; execution starts at address XADR ($0083). The RAM addresses between $0050 and $0082 are used by the loader and are therefore not available to the user during serial loading/executing. Refer to Figure C-7 shows a suitable circuit. Figure C-9 shows address and data bus timing.
C.5.4
RAM parallel bootstrap load and execute
The RAM bootstrap program will start loading the RAM with external data (e.g. from a 2564 or 2764 EPROM). Before loading a new byte, the state of the PD4/AN4 pin is checked; if this pin goes to level `0', or if the RAM is full, then control is given to the loaded program at address $0050. If the data is supplied by a parallel interface, handshaking will be provided by PC5 and PC6 according to Figure C-10. If the data comes from an external EPROM, the handshake can be disabled by connecting together PC5 and PC6. Figure C-8 shows a circuit that can be used to load the RAM with short test programs. Up to 8 programs can be loaded in turn from the EPROM. Selection is accomplished by means of the switches connected to the EPROM higher address lines (A8 through A10). If the user program sets PC0 to level `1', the external EPROM will be disabled, rendering both port A outputs and port B inputs available. The EPROM parallel bootstrap loader circuit (Figure C-6) can also be used, provided VPP is tied to VDD. The high order address lines will be at zero. The LEDs will stay off.
14
Freescale C-14 MC68HC705B5 MC68HC05B6 Rev. 4.1
P1
1 2 3
RESET 100k 1k
RUN 1N914 1.0F +
GND +5V VPP
10nF
+ 47F
22 19
8
10
1N914
TCAP1 VRH VDD IRQ OSC1
10M 47F +
18 RESET
Red LED 0.01F 470 470 Green LED
OSC2 20 21 PLMA
22pF 4.0 MHz 22pF
PLMB
Erase check Green -- EPROM erased Red -- EPROM not erased
PD3
MC68HC705B5
Serial boot
PD4
Green -- programming OK Red -- programming error 1N5819 BC309C Serial boot Erase check 1 k
39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PD0 PD1 PD2 PD5 PD6 PD7
10 k
VPP6
12 k 4k7
PC7
4k7
BC239C
1nF
+
9600 BD 8-bit no parity
8 5 7 3 2 1 2 x 3K
22F + 2
+5V
16 1 3 4 5 12 11 + 22F + 22F
RS232 Connector
22F + 6 13 14
MAX 232
14 13 12 5 4 3
PC6 PC5 PC4 PC3 PC2 PC1 PC0
43 44 45 46 47 48 49
50 RDI 52 TDO VSS 41
15
23 TCAP2 2 TCMP1 1 TCMP2 51 SCLK 40 NC VRL
7
Note:
A minimum VDD voltage must be applied to the VPP6 pin at all times, including power-on, as a lower voltage could damage the device. Unless otherwise stated, EPROM programming is guaranteed at ambient (25C) temperature only
14
Figure C-7 EPROM (RAM) serial bootstrap schematic diagram
MC68HC05B6 Rev. 4.1
MC68HC705B5
Freescale C-15
P1
RESET 100k 1N914 1k 1.0F + RUN 1N914
1
GND +5V
100F VDD OSC1
+
2
TCAP1 IRQ RESET
10M
OSC2
4.0 MHz 22pF 22pF
0.01F
PD4 VPP6
MC68HC705B5
+5V 18 x 100 k
+5V
+5V 16 x 100k
1
26
27
28 10 9 8 7 6 5 4 3 11 12 13 15 16 17 18 19
VPP NC PGM VCC 20 CE 23 A11 2 A12 A0 A1 A2 A3 A4 A5 A6 A7 D0 D1 D2 D3 D4 D5 D6 D7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB6 PB7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
+5V
U1 2764
3 x 4.7k 25 24 21 A8 A9 A10 GND 14
OE 22
NC TCAP2 TCMP2 TCMP1 PLMB PLMA SCLK TDO RDI VRH VRL PD7 PD6 PD5 PD3 PD2 PD1 PD0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 VSS
14
Figure C-8 RAM parallel bootstrap schematic diagram Freescale C-16 MC68HC705B5 MC68HC05B6 Rev. 4.1
C.5.5
Bootstrap loader timing diagrams
tCOOE Address tADE tDHE tADE
tCOOE
tCOOE
tCDDE
tDHE
tADE
tDHE
tADE
tDHE
Data tADE max (address to data delay) tDHA min (data hold time) tCOOE (load cycle time) tCDDE (programming cycle time) 5 machine cycles 14 machine cycles 117 machine cycles < tCOOE < 150 machine cycles tCOOE + tPROG (5ms nominal)
1 machine cycle = 1/(2f0(Xtal))
Figure C-9 EPROM parallel bootstrap loader timing diagram
14
MC68HC05B6 Rev. 4.1 MC68HC705B5 Freescale C-17
tCR
Address PC5 out tHO tADR tDHR
Data PC6 in tHI max
PD4
tEXR max
tADR max (address to data delay; PC6=PC5) tDHR min (data hold time) tCR (load cycle time; PC6=PC5) tHO (PC5 handshake out delay) tHI max (PC6 handshake in, data hold time) tEXR max (max delay for transition to be recognised during this cycle; PC6=PC5 1 machine cycle = 1/(2f0(Xtal))
16 machine cycles 4 machine cycles 49 machine cycles 5 machine cycles 10 machine cycles 30 machine cycles
Figure C-10
RAM parallel loader timing diagram
14
Freescale C-18 MC68HC705B5 MC68HC05B6 Rev. 4.1
C.6
Note:
DC electrical characteristics
The complete table of DC electrical characteristics can be found in Section 11.2. The values contained in the following table should be used in conjunction with those quoted in that section.
Table C-4 Additional DC electrical characteristics for MC68HC705B5
(VDD = 5 Vdc 10%, VSS = 0 Vdc, TA = 25C) Characteristic Input current Port B and port C pull-down (VIN =VIH) EPROM absolute maximum voltage EPROM programming voltage EPROM programming current EPROM read voltage Symbol IRPD VPP6 max VPP6 IPP6 VPP6R VDD 15.0 -- VDD Min Typ 80 -- 15.5 -- VDD 18 16 18 VDD Max Unit A V V mA V
C.7
Note:
Control timing
The complete table of control timing can be found in Section 11.4. The values contained in the following table should be used in conjunction with those quoted in that section.
Table C-5 Additional control timing for MC68HC705B5
(VDD = 5 Vdc 10%, VSS = 0 Vdc, TA = 25 C) Characteristic EPROM programming time Symbol tPROG Min 5 Typ -- Max 20 Unit ms
14
MC68HC05B6 Rev. 4.1 MC68HC705B5 Freescale C-19
THIS PAGE LEFT BLANK INTENTIONALLY
14
Freescale C-20 MC68HC705B5 MC68HC05B6 Rev. 4.1
D
MC68HC05B16
Maskset errata This errata section outlines the differences between previously available masksets (D20J, F62J and G28F) and all other masksets. Unless otherwise stated, the main body of Appendix D refers to all these other masksets with any differences being noted in this errata section. * Certain MC68HC05B16 masksets contain the same oscillator circuitry as the MC68HC05B6 (see Section 2.5.8.3). These are denoted by D20J, F62J and G28F.
The MC68HC05B16 is a device similar to the MC68HC05B6, but with increased RAM, ROM and self-check ROM sizes. The entire MC68HC05B6 data sheet, including the electrical characteristics, applies to the MC68HC05B16, with the exceptions outlined in this appendix.
D.1
* * * * *
Features
15 kbytes User ROM 352 bytes of RAM 496 bytes self-check ROM 52-pin PLCC, 56-pin SDIP and 64-pin QFP packages High speed version available
14
MC68HC05B6 Rev. 4.1 MC68HC05B16 Freescale D-1
Table D-1 Mode of operation selection
IRQ pin VSS to VDD 2VDD 2VDD 2VDD TCAP1 pin VSS to VDD VDD VDD VDD PD3 X 0 1 1 PD4 X X 0 1 Mode Single chip Self check Serial RAM loader Jump to any address
D.2
Self-check routines
The self-check routines for the MC68HC05B16 are identical to those of the MC68HC05B4 with the following exception. The count byte on the MC68HC05B16 can be any value up to 256 ($00). The first 176 bytes are loaded into RAM I and the remainder is loaded into RAM II starting at $0250.
14
Freescale D-2 MC68HC05B16 MC68HC05B6 Rev. 4.1
VPP1
Charge pump
496 bytes self-check ROM
Port A
256 bytes EEPROM
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2/ECLK PC3 PC4 PC5 PC6 PC7 TCMP1 TCMP2 TCAP1 TCAP2 RDI SCLK TDO PLMA D/A PLMB D/A
15120 bytes ROM Port B
RESET IRQ OSC2 OSC1
COP watchdog
Oscillator
VDD VSS
M68HC05 CPU 16-bit timer Port D
PD0/AN0 PD1/AN1 PD2/AN2 PD3/AN3 PD4/AN4 PD5/AN5 PD6/AN6 PD7/AN7 VRH VRL
8-bit A/D converter
SCI
PLM
Figure D-1 MC68HC05B16 block diagram
Port C
/ 2 / /32
352 bytes static RAM
14
MC68HC05B6 Rev. 4.1 MC68HC05B16 Freescale D-3
D.3
External clock
When using an external clock the OSC1 and OSC2 pins should be driven in antiphase, as shown in Figure D-2. The tOXOV or tILCH specifications (see Section 11.4) do not apply when using an external clock input. The equivalent specification of the external clock source should be used in lieu of tOXOV or tILCH.
L OSC1
C1
RS OSC2
MCU OSC1 OSC2
C0
(b) Crystal equivalent circuit COSC1 COSC2 MCU (a) Crystal/ceramic resonator oscillator connections OSC1 OSC2
External clock
NC
(c) External clock source connections Crystal 2MHz RS(max) C0 C1 COSC1 COSC2 RP Q 400 5 8 4MHz 75 7 12 Unit pF F pF pF M -- RS(typ) C0 C1 COSC1 COSC2 RP Q Ceramic resonator 2 - 4MHz 10 40 4.3 30 30 1 - 10 1250 Unit pF pF pF pF M --
15 - 40 15 - 30 15 - 30 15 - 25 10 30 000 10 40 000
(d) Typical crystal and ceramic resonator parameters
Figure D-2 Oscillator connections
14
Freescale D-4 MC68HC05B16 MC68HC05B6 Rev. 4.1
MC68HC05B16 $0000 I/O (32 bytes) $0020 Page 0 User ROM (48 bytes)
Registers
Port A data register Port B data register Port C data register Port D input data register Port A data direction register Port B data direction register Port C data direction register EEPROM/ECLK control register $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F
$0050 RAM1 (176 bytes) Stack Options register Unprotected (31 bytes) EEPROM (256 bytes) Protected (224 bytes) $0200 $0250 $0300 $3DFE $3E00 Self-check ROM (496 bytes) $3FF0 $3FF2-3 SCI Timer overflow $3FF4-5 $3FF6-7 Timer output compare 1& 2 $3FF8-9 Timer input capture 1 & 2 External IRQ $3FFA-B $3FFC-D SWI $3FFE-F Reset/power-on reset RAM11 (176 bytes) User ROM (15104 bytes)
A/D data register A/D status/control register Pulse length modulation A Pulse length modulation B Miscellaneous register SCI baud rate register SCI control register 1 SCI control register 2 SCI status register SCI data register Timer control register Timer status register Capture high register 1 Capture low register 1 Compare high register 1 Compare low register 1 Counter high register Counter low register Alternate counter high register Alternate counter low register Capture high register 2 Capture low register 2 Compare high register 2 Compare low register 2
$00C0 $0100 $0101 $0120
User vectors (14 bytes) Reserved
Options register
$0100
Figure D-3 Memory map of the MC68HC05B16
14
MC68HC05B6 Rev. 4.1 MC68HC05B16 Freescale D-5
Table D-2 Register outline
Register name Port A data (PORTA) Port B data (PORTB) Port C data (PORTC) Port D data (PORTD) Port A data direction (DDRA) Port B data direction (DDRB) Port C data direction (DDRC) EEPROM/ECLK control A/D data (ADDATA) A/D status/control (ADSTAT) Pulse length modulation A (PLMA) Pulse length modulation B (PLMB) Miscellaneous SCI baud rate (BAUD) SCI control 1 (SCCR1) SCI control 2 (SCCR2) SCI status (SCSR) SCI data (SCDR) Timer control (TCR) Timer status (TSR) Input capture high 1 Input capture low 1 Output compare high 1 Output compare low 1 Timer counter high Timer counter low Alternate counter high Alternate counter low Input capture high 2 Input capture low 2 Output compare high 2 Output compare low 2 Options (OPTR)(3) Address bit 7 $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C POR(1) INTP $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F $0100 EE1P ICIE ICF1 OCIE OCF1 TOF ICF2 OCF2 SPC1 R8 TIE TDRE SPC0 T8 TCIE TC RIE RDRF INTN SCT1 INTE SCT0 M ILIE IDLE SFA SCT0 TE OR SFB SCR2 RE NF SM SCR1 RWU FE COCO ADRC ADON 0 CH3 CH2 CH1 CH0 0 0 0 0 PD7 PD6 PD5 PD4 PD3 PC2/ ECLK PD2 PD1 PD0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Undefined Undefined Undefined Undefined 0000 0000 0000 0000 0000 0000 ECLK E1ERA E1LAT E1PGM 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 WDOG(2) ?001 000? SCR0 00uu uuuu LBCL SBK Undefined 0000 0000 1100 000u 0000 0000 TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0 Undefined Undefined Undefined Undefined Undefined 1111 1111 1111 1100 1111 1111 1111 1100 Undefined Undefined Undefined Undefined SEC Not affected
WAKE CPOL CPHA
(1) This bit is set each time there is a power-on reset. (2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1=watchdog enabled, 0=watchdog disabled. (3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.
14
Freescale D-6 MC68HC05B16 MC68HC05B6 Rev. 4.1
E
MC68HC705B16
To ensure correct operation of the MC68HC705B16 after power-on, the device must be reset a second time after power-on. This can be done in software using the MC68HC705B16 watchdog. The following software sub-routine should be used: RESET2 BSET 0, $0C STOP Start watchdog STOP causes immediate watchdog system reset
The interrupt vector at $3FF0 and $3FF1 must be initialised with the RESET2 address value.
The MC68HC705B16 is a device similar to the MC68HC05B6, but with increased RAM and 15 kbytes of EPROM instead of 6 kbytes of ROM. In addition, the self-check routines available in the MC68HC05B6 are replaced by bootstrap firmware. The MC68HC705B16 is an OTPROM (one-time programmable ROM) version of the MC68HC05B16, meaning that once the application program has been loaded in the EPROM it can never be erased. The entire MC68HC05B6 data sheet applies to the MC68HC705B16, with the exceptions outlined in this appendix.
14
MC68HC05B6 Rev. 4.1 MC68HC705B16 Freescale E-1
E.1
* * * * * * *
Features
15 kbytes EPROM 352 bytes of RAM 576 bytes bootstrap ROM Simultaneous programming of up to 8 bytes of EPROM Optional pull-down resistors available on all port B and port C pins 52-pin PLCC and 64-pin QFP packages High speed version not available
VPP1
Charge pump
576 bytes bootstrap ROM
Port A
256 bytes EEPROM
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2/ECLK PC3 PC4 PC5 PC6 PC7 TCMP1 TCMP2 TCAP1 TCAP2 RDI SCLK TDO PLMA D/A PLMB D/A
VPP6
15168 bytes EPROM Port B
RESET IRQ OSC2 OSC1
COP watchdog
Oscillator
VDD VSS
M68HC05 CPU 16-bit timer Port D
PD0/AN0 PD1/AN1 PD2/AN2 PD3/AN3 PD4/AN4 PD5/AN5 PD6/AN6 PD7/AN7 VRH VRL
8-bit A/D converter
SCI
PLM
Figure E-1 MC68HC705B16 block diagram Note: The electrical characteristics of the MC68HC05B6 as provided in Section 11 do not apply to the MC68HC705B16. Data specific to the MC68HC705B16 can be found in this appendix.
14
Freescale E-2
MC68HC705B16
Port C
/ 2 / / 32
352 bytes static RAM
MC68HC05B6 Rev. 4.1
MC68HC705B16 $0000 I/O (32 bytes) $0020 Page 0 User EPROM (48 bytes)
Registers
Port A data register Port B data register Port C data register Port D input data register Port A data direction register Port B data direction register Port C data direction register E/EEPROM/ECLK control register $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F
$0050 RAM1 (176 bytes) Stack Options register Unprotected (31 bytes) EEPROM (256 bytes) Protected (224 bytes) $0200 $0250 $0300 $3DFE $3DFF $3E00 Bootstrap ROM1 (80 bytes) RAM11 (176 bytes) User EPROM (15104 bytes) Mask option register Bootstrap ROM11 (496 bytes) $3FF0-1 $3FF2-3 SCI Timer overflow $3FF4-5 $3FF6-7 Timer output compare 1& 2 $3FF8-9 Timer input capture 1 & 2 External IRQ $3FFA-B $3FFC-D SWI $3FFE-F Reset/power-on reset
A/D data register A/D status/control register Pulse length modulation A Pulse length modulation B Miscellaneous register SCI baud rate register SCI control register 1 SCI control register 2 SCI status register SCI data register Timer control register Timer status register Capture high register 1 Capture low register 1 Compare high register 1 Compare low register 1 Counter high register Counter low register Alternate counter high register Alternate counter low register Capture high register 2 Capture low register 2 Compare high register 2 Compare low register 2
$00C0 $0100 $0101 $0120
User vectors (14 bytes) Reserved
Options register Mask option register
$0100 $3DFE
Figure E-2 Memory map of the MC68HC705B16
14
MC68HC05B6 Rev. 4.1 MC68HC705B16 Freescale E-3
Table E-1 Register outline
Register name Port A data (PORTA) Port B data (PORTB) Port C data (PORTC) Port D data (PORTD) Port A data direction (DDRA) Port B data direction (DDRB) Port C data direction (DDRC) EPROM/EEPROM/ECLK control A/D data (ADDATA) A/D status/control (ADSTAT) Pulse length modulation A (PLMA) Pulse length modulation B (PLMB) Miscellaneous SCI baud rate (BAUD) SCI control 1 (SCCR1) SCI control 2 (SCCR2) SCI status (SCSR) SCI data (SCDR) Timer control (TCR) Timer status (TSR) Input capture high 1 Input capture low 1 Output compare high 1 Output compare low 1 Timer counter high Timer counter low Alternate counter high Alternate counter low Input capture high 2 Input capture low 2 Output compare high 2 Output compare low 2 Options (OPTR)(3) Mask option register (MOR)(4) Address bit 7 $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C POR(1) INTP $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F $0100 $3DFE EE1P ICIE ICF1 OCIE OCF1 TOF ICF2 OCF2 SPC1 R8 TIE TDRE SPC0 T8 TCIE TC RIE RDRF INTN SCT1 INTE SCT0 M ILIE IDLE SFA SCT0 TE OR SFB SCR2 RE NF SM SCR1 RWU FE COCO ADRC ADON 0 CH3 CH2 CH1 CH0 PD7 PD6 PD5 PD4 PD3 PC2/ ECLK PD2 PD1 PD0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Undefined Undefined Undefined Undefined 0000 0000 0000 0000 0000 0000 E6LAT E6PGM ECLK E1ERA E1LAT E1PGM 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 WDOG(2) ?001 000? SCR0 00uu uuuu LBCL SBK Undefined 0000 0000 1100 000u 0000 0000 TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0 Undefined Undefined Undefined Undefined Undefined 1111 1111 1111 1100 1111 1111 1111 1100 Undefined Undefined Undefined Undefined SEC Not affected RTIM RWAT WWAT PBPD PCPD Not affected
WAKE CPOL CPHA
(1) This bit is set each time there is a power-on reset. (2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1=watchdog enabled, 0=watchdog disabled. (3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits. (4) This register is implemented in EPROM; therefore reset has no effect on the individual bits.
14
Freescale E-4
MC68HC705B16
MC68HC05B6 Rev. 4.1
E.2
External clock
When using an external clock the OSC1 and OSC2 pins should be driven in antiphase (see Figure D-2). The tOXOV or tILCH specifications (see Section E.8) do not apply when using an external clock input. The equivalent specification of the external clock source should be used in lieu of tOXOV or tILCH.
E.3
EPROM
The MC68HC705B16 memory map is given in Figure E-2. The device has a total of 15168 bytes of EPROM (including 14 bytes for User vectors) and 256 bytes of EEPROM. The EPROM array is supplied by the VPP6 pin in both read and program modes. Typically the user's software would be loaded into a programming board where VPP6 is controlled by one of the bootstrap loader routines. It would then be placed in an application where no programming occurs. In this case the VPP6 pin should be hardwired to VDD. Warning: A minimum VDD voltage must be applied to the VPP6 pin at all times, including power-on. Failure to do so could result in permanent damage to the device. Unless otherwise stated, EPROM programming is guaranteed at ambient (25C) temperature only.
E.3.1
EPROM read operation
The execution of a program in the EPROM address range or a load from the EPROM are both read operations. The E6LAT bit in the EPROM/EEPROM control register should be cleared to `0' which automatically resets the E6PGM bit. In this way the EPROM is read like a normal ROM. Reading the EPROM with the E6LAT bit set will give data that does not correspond to the actual memory content. As interrupt vectors are in EPROM, they will not be loaded when E6LAT is set. Similarly, the bootstrap ROM routines cannot be executed when E6LAT is set. In read mode, the VPP6 pin must be at the VDD level. When entering the STOP mode, the EPROM is automatically set to the read mode. Note: An erased byte reads as $00.
E.3.2
EPROM program operation
Typically the EPROM will be programmed by the bootstrap routines resident in the on-chip ROM. However, the user program can be used to program some EPROM locations if the proper procedure is followed. In particular, the programming sequence must be running in RAM, as the
14
MC68HC05B6 Rev. 4.1
MC68HC705B16
Freescale E-5
EPROM will not be available for code execution while the E6LAT bit is set. The VPP6 switching must occur externally after the E6PGM bit is set, for example under control of a signal generated on a pin by the programming routine. Note: When the part becomes a PROM, only the cumulative programming of bits to logic `1' is possible if multiple programming is made on the same byte.
To allow simultaneous programming of up to eight bytes, these bytes must be in the same group of addresses which share the same most significant address bits; only the three least significant bits can change.
E.3.3
EPROM/EEPROM/ECLK control register
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset
EPROM/EEPROM/ECLK control
$0007
E6LAT E6PGM ECLK E1ERA E1LAT E1PGM 0000 0000
E6LAT -- EPROM programming latch enable bit 1 (set) - Address and up to eight data bytes can be latched into the EPROM for further programming providing the E6PGM bit is cleared. Data can be read from the EPROM or firmware ROM; the E6PGM bit is reset to zero when E6LAT is `0'.
0 (clear) -
STOP, power-on and external reset clear the E6LAT bit. Note: After the tERA1 erase time or tPROG1 programming time, the E6LAT bit has to be reset to zero in order to clear the E6PGM bit.
E6PGM -- EPROM program enable bit This bit is the EPROM program enable bit. It can be set to `1' to enable programming only after E6LAT is set and at least one byte is written to the EPROM. It is not possible to clear this bit using software but clearing E6LAT will always clear E6PGM. Table E-2 EPROM control bits description
E6LAT E6PGM 0 1 1 0 0 1 Description Read/execute in EPROM Ready to write address/data to EPROM programming in progress
14
Note:
The E6PGM bit can never be set while the E6LAT bit is at zero.
Freescale E-6
MC68HC705B16
MC68HC05B6 Rev. 4.1
ECLK See Section 4.3. E1ERA -- EEPROM erase/programming bit Providing the E1LAT and E1PGM bits are at logic one, this bit indicates whether the access to the EEPROM is for erasing or programming purposes. 1 (set) - An erase operation will take place. A programming operation will take place.
0 (clear) -
Once the program/erase EEPROM address has been selected, E1ERA cannot be changed. E1LAT -- EEPROM programming latch enable bit 1 (set) - Address and data can be latched into the EEPROM for further program or erase operations, providing the E1PGM bit is cleared. Data can be read from the EEPROM. The E1ERA bit and the E1PGM bit are reset to zero when E1LAT is `0'.
0 (clear) -
STOP, power-on and external reset clear the E1LAT bit. Note: After the tERA1 erase time or tPROG1 programming time, the E1LAT bit has to be reset to zero in order to clear the E1ERA bit and the E1PGM bit.
E1PGM -- EEPROM charge pump enable/disable 1 (set) - Internal charge pump generator switched on. Internal charge pump generator switched off.
0 (clear) -
When the charge pump generator is on, the resulting high voltage is applied to the EEPROM array. This bit cannot be set before the data is selected, and once this bit has been set it can only be cleared by clearing the E1LAT bit. A summary of the effects of setting/clearing bits 0, 1 and 2 of the control register are given in Table E-3.
Table E-3 EEPROM control bits description
E1ERA 0 0 0 1 1 E1LAT E1PGM 0 1 1 1 1 0 0 1 0 1 Read condition Ready to load address/data for program/erase Byte programming in progress Ready for byte erase (load address) Byte erase in progress Description
Note:
The E1PGM and E1ERA bits are cleared when the E1LAT bit is at zero.
14
Freescale E-7
MC68HC05B6 Rev. 4.1
MC68HC705B16
E.3.4
Mask option register
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset
Mask option register (MOR)(1)
$3DFE
RTIM RWAT WWAT PBPD PCPD Not affected
(1) This register is implemented in EPROM; therefore reset has no effect on the individual bits.
RTIM -- Reset time This bit can modify the time tPORL, where the RESET pin is kept low after a power-on reset. 1 (set) - tPORL = 16 cycles. tPORL = 4064 cycles.
0 (clear) -
RWAT -- Watchdog after reset This bit can modify the status of the watchdog counter after reset. Usually, the watchdog system is disabled after power-on or external reset but when this bit is set, it will be active immediately after the following resets (except in bootstrap mode). WWAT -- Watchdog during WAIT mode This bit can modify the status of the watchdog counter in WAIT mode. Normally, the watchdog system is disabled in WAIT mode but when this bit is set, the watchdog will be active in WAIT mode. PBPD -- Port B pull-down This bit, when programmed, connects a resistive pull-down on each pin of port B. This pull-down, RPD, is active on a given pin only while it is an input. PCPD -- Port C pull-down This bit, when programmed, connects a resistive pull-down on each pin of port C. This pull-down, RPD, is active on a given pin only while it is an input.
14
Freescale E-8 MC68HC705B16 MC68HC05B6 Rev. 4.1
E.3.5
EEPROM options register (OPTR)
Address Options (OPTR)(1) $0100 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 EE1P bit 0 State on reset
SEC Not affected
(1) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.
EE1P - EEPROM protect bit In order to achieve a higher degree of protection, the EEPROM is effectively split into two parts, both working from the VPP1 charge pump. Part 1 of the EEPROM array (32 bytes from $0100 to $011F) cannot be protected; part 2 (224 bytes from $0120 to $01FF) is protected by the EE1P bit in the options register. 1 (set) - Part 2 of the EEPROM array is not protected; all 256 bytes of EEPROM can be accessed for any read, erase or programming operations. Part 2 of the EEPROM array is protected; any attempt to erase or program a location will be unsuccessful.
0 (clear) -
When this bit is set to 1 (erased), the protection will remain until the next power-on or external reset. EE1P can only be written to `0' when the E1LAT bit in the EEPROM control register is set. Note: The EEPROM1 protect function is disabled while in bootstrap mode.
SEC -- Secure bit This bit allows the EPROM and EEPROM1 to be secured from external access. When this bit is in the erased state (set), the EPROM and EEPROM1 content is not secured and the device may be used in non user mode. When the SEC bit is programmed to `zero', the EPROM and EEPROM1 content is secured by prohibiting entry to the non user mode. To deactivate the secure bit, the EPROM has to be erased by exposure to a high density ultraviolet light, and the device has to be entered into the EPROM erase verification mode with PD1 set. When the SEC bit is changed, its new value will have no effect until the next power-on or external reset. 1 (set) - EEPROM/EPROM not protected. EEPROM/EPROM protected.
0 (clear) -
14
MC68HC05B6 Rev. 4.1 MC68HC705B16 Freescale E-9
E.4
Bootstrap mode
The 432 bytes of self-check firmware on the MC68HC05B6 are replaced by 576 bytes of bootstrap firmware. A detailed description of the modes of operation within bootstrap mode is given below. The bootstrap program in mask ROM address locations $0200 to $024F and $3E00 to $3FEF can be used to program the EPROM and the EEPROM, to check if the EPROM is erased or to load and execute data in RAM. After reset, while going to the bootstrap mode, the vector located at address $3FEE and $3FEF (RESET) is fetched to start execution of the bootstrap program. To place the part in bootstrap mode, the IRQ pin should be at + 9V with the TCAP1 pin `high' during transition of the RESET pin from low to high. The hold time on the IRQ and TCAP1 pins is two clock cycles after the external RESET pin is brought high. When the MC68HC705B16 is placed in the bootstrap mode, the bootstrap reset vector is fetched and the bootstrap firmware starts to execute. Table E-4 shows the conditions required to enter each level of bootstrap mode on the rising edge of RESET.
Table E-4 Mode of operation selection
IRQ pin VSS to VDD + 9 Volts + 9 Volts + 9 Volts + 9 Volts + 9 Volts x = Don't care TCAP1 pin PD1 PD2 PD3 PD4 VSS to VDD VDD VDD VDD VDD VDD x 0 1 1 x x x 0 0 0 x x x x 0 1 0 1 x 0 0 0 1 1 Single chip Erased EPROM verification (EEV) Erased EPROM verification; erase EEPROM; EPROM/EEPROM parallel program/verify Erased EPROM verification; erase EEPROM; EPROM/EEPROM/ RAM serial bootstrap load and execute RAM parallel bootstrap load and execute (if SEC bit = 1) Serial EPROM/EEPROM/RAM bootloader (if SEC = 1) Mode
The bootstrap program first copies part of itself in RAM (except `RAM parallel load'), as the program cannot be executed in ROM during verification/programming of the EPROM. It then sets the TCMP1 output to a logic high level.
14
Freescale E-10 MC68HC705B16 MC68HC05B6 Rev. 4.1
Reset
IRQ at 9V? Y TCAP1 set? Y
N Y N SEC bit active? N
User mode
Non-user mode
Bootstrap mode
Erased EPROM verification
A Y PD4 set? N PD2 set? Y N EPROM erased? N Y Green LED on
Non-user mode
Red LED on EPROM not erased
N
PD1 set? Y
B
Y
PD3 set? N
Parallel E/EEPROM bootstrap
Red LED on N
Bulk erase EEPROM1
Program EPROM; parallel load; green LED flashes
EEPROM1 erased? Y
Programming OK? N Red LED on
Y
Green LED on EPROM verified
Red LED off
Bad EPROM programming
Figure E-3 Modes of operation flow chart (1 of 2)
14
Freescale E-11
MC68HC05B6 Rev. 4.1
MC68HC705B16
Red LED flashes
Y
SEC bit set? N
A
N
Parallel bootstrap RAM
PD3 set?
Serial E/EEPROM (RAM) bootstrap
Y N
PD4 set? Y Load next RAM byte
B
Transmit last four programmed locations
N
RAM1 full? Y Execute RAM program at $0050
Receive address
Receive four data
Y
Negative address? N
Green LED on
Program E/EEPROM data at address; green LED flashes
Execute RAM program at $008B
Figure E-4 Modes of operation flow chart (2 of 2)
14
Freescale E-12 MC68HC705B16 MC68HC05B6 Rev. 4.1
E.4.1
Erased EPROM verification
If a non $00 byte is detected, the red LED is turned on and the routine stops (see Figure E-3 and Figure E-4). Only when the entire EPROM content is verified as erased does the green LED switch on. PD1 is then checked. If PD1=0, the bootstrap program stops here and no programming occurs until such time as a high level is sensed on PD1. If PD1=1, the bootstrap program proceeds to erase the EEPROM1 for a nominal 100 ms (4.0 MHz crystal). It is then checked for complete erasure; if a non $FF byte is detected, the red LED is turned on, and erase is performed a second time, and so on until total erasure is verified. At this point, both EPROM and EEPROM1 are completely erased and the security bit is cleared. The programming operation can then be performed. A schematic diagram of the circuit required for erased EPROM verification is shown in Figure E-7.
E.4.2
EPROM/EEPROM parallel bootstrap
Before the parallel bootstrap routines begin, the erased EPROM verification program is executed as described in Section E.4.1. When PD2=0, the programming time is set to 5 milliseconds with the bootstrap program and verify for the EPROM taking approximately 15 seconds. The EPROM is loaded in increasing address order with non EPROM segments being skipped by the loader. Simultaneous programming is performed by reading eight bytes of data before actual programming is performed, thus the loading time of the internal EPROM is divided by eight. Parallel data is entered through Port A, while the 14-bit address is output on port B, PC0 to PC4 and TCMP2. If the data comes from an external EPROM, the handshake can be disabled by connecting together PC5 and PC6. If the data is supplied by a parallel interface, handshaking will be provided by PC5 and PC6 according to the timing diagram of Figure E-5 (see also Figure E-6). During programming, the green LED will flash at about 3 Hz. Upon completion of the programming operation, the contents of the EPROM and EEPROM1 are checked against the external data source. If programming is verified the green LED stays on, while an error will cause the red LED to be turned on. Figure E-7 is a schematic diagram of a circuit that can be used to program the EPROM or to load and execute data in the RAM. Note: The entire EPROM and EEPROM1 can be loaded from the external source; if it is desired to leave a segment undisturbed, the data for this segment should be all zeros for EPROM data and all $FFs for EEPROM1 data.
14
MC68HC05B6 Rev. 4.1 MC68HC705B16 Freescale E-13
Address
HDSK out (PC5) Data
HDSK in (PC6) F29
Data read
Data read
Figure E-5 Timing diagram with handshake
tCOOE Address tADE tDHE tADE
tCOOE
tCOOE
tCDDE
tDHE
tADE
tDHE
tADE
tDHE
Data tADE max (address to data delay) tDHA min (data hold time) tCOOE (load cycle time) tCDDE (programming cycle time) 5 machine cycles 14 machine cycles 117 machine cycles < tCOOE < 150 machine cycles tCOOE + tPROG (5ms nominal for EPROM; 10ms for EEPROM1)) 1 machine cycle = 1/(2f0(Xtal))
Figure E-6 Parallel EPROM loader timing diagram
14
Freescale E-14 MC68HC705B16 MC68HC05B6 Rev. 4.1
P1
RESET 100k 1N914 1k 1.0F + RUN 1N914 100F +
1 2 3
GND +5V VPP
TCAP1 VRH VDD IRQ RESET OSC1 OSC2 RDI VRL TCAP2 PD7 PD6 PD5 PD3 PD2 PD1 PD0
4.0 MHz 22pF 22pF 47F +
red LED 0.01F 470 470 Boot red LED -- programming failed green LED -- programming OK Erase check green LED -- EPROM erased red LED -- EPROM not erased green LED
NC TCMP1 VPP1 PLMA PLMB
Erase check & boot
EPROM erase check
+5V 1 27 28 26 10 9 8 7 6 5 4 3 11 12 13 15 16 17 18 19
MC68HC705B16 MCU
PD4
RAM EPROM 1N5819 1 k BC309C
VPP PGM VCC A13 A0 A1 A2 A3 A4 20 CE A5 A6 27C128 A7 D0 D1 D2 D3 D4 D5 D6 D7 GND 14 OE 22
SCLK TDO TCMP2 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 VSS VPP6
10k
12 k 4k7
PC7
4k7
BC239C
1nF
+
+5V
100 k HDSK out Short circuit if handshake not used
25 24 21 23 2
PC5 PC6 PC4 PC3 PC2 PC1 PC0 A12 A11 A10 A9 A8
A8 A9 A10 A11 A12
HDSK in
Note:
This circuit is recommended for programming only at 25C and not for use in the end application, or at temperatures other than 25C. If used in the end application, VPP6 should be tied to VDD to avoid damaging the device.
14
Figure E-7 EPROM Parallel bootstrap schematic diagram MC68HC05B6 Rev. 4.1 MC68HC705B16 Freescale E-15
E.4.3
EEPROM/EPROM/RAM serial bootstrap
For erased EPROM verification, PD4 must be at `0'. In this case, erased EPROM verification executes as described in Section E.4.1 before control is given to the serial routine. If PD4 is at `1', the program initially checks the state of the security bit. If the security bit is active (`0'), the program will not enter serial bootstrap and the red LED will flash. Otherwise the serial bootstrap program will be executed according to Figure E-3 and Figure E-4. The serial routine communicates through the SCI with an external host, typically a PC, by means of an RS232 link at 9600 baud, 8-bit, no parity and full duplex. Refer to Figure E-8 for a schematic diagram of a suitable circuit. Note: Data format is not ASCII, but 8-bit binary, so a complementary program must be run by the host to supply the required format. Such a program is available for the IBM PC from Freescale.
The EPROM bootstrap routines are used to customise the OTP EPROM. To increase the speed of programming the 15 kbytes, four bytes are programmed while the data is simultaneously transmitted back and forward in full duplex. This implies that while 4 bytes are being programmed the next 4 bytes are received and the preceding 4 bytes are echoed. The format accepted by the serial loader is as follows: 1) EPROM locations [address n high] [address n low] [data(n)] [data (n+1)] [data (n+2)] [data (n+3)] Address n must have the two least significant bits at zero so that n, n+1, n+2 and n+3 have identical most significant bits. These blocks of four bytes do not need to be contiguous, as a new address is transmitted for each new group. 2) EEPROM1 locations [address n high] [address n low] [data(n)] [dummy data 1] [dummy data 2] [dummy data 3] The same four byte protocol of data exchange is used, but only the first data value is programmed at address n. The three following dummy data values must be sent to be in agreement with the protocol, but are not significant. The protocol is as follows: 1) The MC68HC705B16 sends the last two bytes programmed to the host as a prompt; this also allows the host to verify that programming has been carried out correctly. 2) In response to the first byte prompt, the host sends the first address byte. 3) After receiving the first address byte, the MC68HC705B16 sends the next byte programmed.
14
Freescale E-16
MC68HC705B16
MC68HC05B6 Rev. 4.1
P1
1 2 3
RESET 100k 1k
RUN 1N914 1.0F +
GND +5V VPP
10nF
+ 47F
22 19
8
10
1N914
TCAP1 VRH VDD IRQ OSC1
47F +
18 RESET
Red LED 0.01F 470 470 Green LED
20 21
PLMA PLMB
OSC2
4.0 MHz 22pF 22pF
U2 MC68HC705B16 MCU (socket)
PD3
Erase check Green LED -- EPROM erased Red LED -- EPROM not erased
Serial boot
PD4
Serial boot Flashing green LED -- programming Green LED -- programming ended
39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 14 13 12 5 4 3
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PD0 PD1 PD2 PD5 PD6 PD7
10k
VPP6
12 k 4k7
PC7
4k7
BC309C
1N5819
Erase check & serial boot
1 k
BC239C
1nF
+
Erase check and serial boot EPROM erase check
9600 BD 8-bit no parity
8 5 7 3 2 1 2 x 3K
22F + 2
+5V
16 1 3 4 5 12 11 + 22F + 22F
PC6 PC5 PC4 PC3 PC2 PC1 PC0
43 44 45 46 47 48 49
RS232 connector
22F + 6 13 14
MAX 232
50 RDI 52 TDO VSS 41
15
VPP1 23 TCAP2 2 TCMP1 1 TCMP2 51 SCLK 40 NC VRL
7
Note:
A minimum VDD voltage must be applied to the VPP6 pin at all times, including power-on, as a lower voltage could damage the device. Unless otherwise stated, EPROM programming is guaranteed at ambient (25C) temperature only
14
Freescale E-17
Figure E-8 RAM/EPROM/EEPROM serial bootstrap schematic diagram
MC68HC05B6 Rev. 4.1
MC68HC705B16
4) The exchange of data continues until the MC68HC705B16 has sent the four data bytes and the host has sent the 2 address data bytes and 4 data bytes. 5) If the data is different from $00 for EPROM or $FF for EEPROM, it is programmed at the address provided, while the next address and bytes are received and the previous data is echoed. 6) Loop to 1. After reset, the MC68HC705B16 serial bootstrap routine will first echo two blocks of four bytes at $00, as no data is programmed yet. If the data received is $00 for EPROM locations or $FF for EEPROM locations, no programming in the EPROM and EEPROM1 takes place, and the contents of the accessed location are returned as a prompt. The entire EPROM/EEPROM memory can be read in this fashion (serial dump). Warning: When using this function with a programmed device, the device must be placed into RAM/EPROM/EEPROM serial bootstrap mode without EPROM erase check (PD4 = 1). Serial RAM loading and execute can be accomplished in this mode. A RAM byte will be written if the address sent by the host in the serial protocol points to the RAM. RAM bytes $008B-$00E3 and $0250-$02ED are available for user test programs. A 10-byte stack resides at the top of RAMI, allowing, for example, one interrupt and two sub-routine levels. The RAM addresses between $0050 and $008A are used by the loader and are therefore not available to the user during serial loading/executing. If the SEC bit is at `1', program execution is triggered by sending a negative (bit 7 set) high address; execution starts at address XADR ($008B). In the RAM bootloader mode, all interrupt vectors are mapped to pseudo-vectors in RAM (see Table E-5). This allows programmers to use their own service-routine addresses. Each pseudo-vector is allowed three bytes of space rather than the two bytes for normal vectors, because an explicit jump (JMP) opcode is needed to cause the desired jump to the user's service routine address.
Table E-5 Bootstrap vector targets in RAM
Vector targets in RAM SCI interrupt Timer overflow Timer output compare Timer input capture IRQ $02EE $02F1 $02F4 $02F7 $02FA $02FD
14
Freescale E-18
SWI
MC68HC705B16
MC68HC05B6 Rev. 4.1
E.4.4
RAM parallel bootstrap
The program first checks the state of the security bit. If the SEC bit is active, i.e. `0', the program will not enter the RAM bootstrap mode and the red LED will flash. Otherwise the RAM bootstrap program will start loading the RAM with external data (e.g. from a 2564 or 2764 EPROM). Before loading a new byte the state of the PD4/AN4 pin is checked. If this pin goes to level `0', or if the RAM is full, then control is given to the loaded program at address $0050. See Figure E-3 and Figure E-4. If the data is supplied by a parallel interface, handshaking will be provided by PC5 and PC6 according to Figure E-9. If the data comes from an external EPROM, the handshake can be disabled by connecting together PC5 and PC6. Figure E-10 provides a schematic diagram of a circuit that can be used to load the RAM with short test programs. Up to 8 programs can be loaded in turn from the EPROM. Selection is accomplished by means of the switches connected to the EPROM higher address lines (A8 through A10). If the user program sets PC0 to level `1', this will disable the external EPROM, thus rendering both port A output and port B input available. The EPROM parallel bootstrap loader schematic can also be used (Figure E-7), provided VPP is at VDD level. The high order address lines will be at zero. The LEDs will stay off.
tCR
Address PC5 out tHO tADR tDHR
Data PC6 in PD4 tHI max tEXR max 16 machine cycles 4 machine cycles 49 machine cycles 5 machine cycles 10 machine cycles 30 machine cycles
tADR max (address to data delay; PC6=PC5) tDHR min (data hold time) tCR (load cycle time; PC6=PC5) tHO (PC5 handshake out delay) tHI max (PC6 handshake in, data hold time) tEXR max (max delay for transition to be recognised during this cycle; PC6=PC5 1 machine cycle = 1/(2f0(Xtal))
Figure E-9 Parallel RAM loader timing diagram
14
Freescale E-19
MC68HC05B6 Rev. 4.1
MC68HC705B16
E.4.4.1
Jump to start of RAM ($0050)
PD4 must be high during the first 49 program cycles and pulled low before the 68th cycle for immediate jump execution at address $0050.
P1
RESET 100k 1N914 1k 1.0F + RUN 1N914
1
GND +5V
100F VDD OSC1
+
2
TCAP1 IRQ RESET
OSC2
0.01F 22pF 4.0 MHz 22pF
PD4 VPP6
U2 MC68HC705B16 MCU (socket)
VPP1 NC TCAP2 TCMP2 TCMP1 PLMB PLMA SCLK TDO RDI VRH VRL PD7 PD6 PD5 PD3 PD2 PD1 PD0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 VSS
+5V 18 x 100 k
+5V 16 x 100k
1
26
27
28 10 9 8 7 6 5 4 3 11 12 13 15 16 17 18 19
VPP NC PGM VCC 20 CE 23 A11 2 A12 A0 A1 A2 A3 A4 A5 A6 A7 D0 D1 D2 D3 D4 D5 D6 D7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB6 PB7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
+5V
U1 2764
3 x 4.7k 25 24 21 A8 A9 A10 GND 14
OE 22
Figure E-10 RAM parallel bootstrap schematic diagram
14
Freescale E-20 MC68HC705B16 MC68HC05B6 Rev. 4.1
E.5
Absolute maximum ratings
Table E-6 Absolute maximum ratings
Rating Supply voltage(1) Input voltage (Except VPP1 and VPP6) Input voltage - Self-check mode (IRQ pin only) Operating temperature range - Standard (MC68HC705B16) - Extended (MC68HC705B16C) - Industrial (MC68HC705B16V) - Automotive (MC68HC705B16M) Storage temperature range Current drain per pin (excluding VDD and VSS)(2) - Source - Sink (1) All voltages are with respect to VSS. (2) Maximum current drain per pin is for one pin at a time, limited by an external resistor. Symbol VDD VIN VIN TA Value - 0.5 to +7.0 VSS - 0.5 to VDD + 0.5 VSS - 0.5 to 2VDD + 0.5 TL to TH 0 to +70 -40 to +85 -40 to +105 -40 to +125 - 65 to +150 25 45 Unit V V V
C
TSTG ID IS
C mA mA
Note:
This device contains circuitry designed to protect against damage due to high electrostatic voltages or electric fields. However, it is recommended that normal precautions be taken to avoid the application of any voltages higher than those given in the maximum ratings table to this high impedance circuit. For maximum reliability all unused inputs should be tied to either VSS or VDD.
14
MC68HC05B6 Rev. 4.1 MC68HC705B16 Freescale E-21
E.6
DC electrical characteristics
Table E-7 DC electrical characteristics for 5V operation
(VDD = 5 Vdc 10%, VSS = 0 Vdc, TA = TL to TH) Symbol Characteristic(1) Output voltage ILOAD = - 10 A VOH ILOAD = +10 A VOL Output high voltage (ILOAD = 0.8mA) PA0-7, PB0-7, PC0-7, TCMP1, TCMP2 VOH Output high voltage (ILOAD = 1.6mA) VOH TDO, SCLK, PLMA, PLMB Output low voltage (ILOAD = 1.6mA) PA0-7, PB0-7, PC0-7, TCMP1, TCMP2, VOL TDO, SCLK, PLMA, PLMB Output low voltage (ILOAD = 1.6mA) VOL RESET Input high voltage PA0-7, PB0-7, PC0-7, PD0-7, OSC1, VIH IRQ, RESET, TCAP1, TCAP2, RDI Input low voltage VIL PA0-7, PB0-7, PC0-7, PD0-7, OSC1, IRQ, RESET, TCAP1, TCAP2, RDI Supply current(3) RUN (SM = 0) (See Figure 11-1) IDD IDD RUN (SM = 1) (See Figure 11-2) IDD WAIT (SM = 0) (See Figure 11-3) IDD WAIT (SM = 1) (See Figure 11-4) STOP IDD 0 to 70 (standard) IDD - 40 to 85 (extended) IDD - 40 to 105 (industrial) IDD - 40 to 125 (automotive) High-Z leakage current IIL PA0-7, PB0-7, PC0-7, TDO, RESET, SCLK Input current Port B and port C pull-down (VIN =VIH) IRPD Input current (0 to 70) IIN IRQ, OSC1, TCAP1, TCAP2, RDI, PD0/AN0-PD7/AN7 (channel not selected) Input current (- 40 to 125) IIN IRQ, OSC1, TCAP1, TCAP2, RDI, PD0/AN0-PD7/AN7 (channel not selected) Capacitance Ports (as input or output), RESET, TDO, SCLK COUT CIN IRQ, TCAP1, TCAP2, OSC1, RDI CIN PD0/AN0-PD7/AN7 (A/D off) CIN PD0/AN0-PD7/AN7 (A/D on) Min VDD - 0.1 -- VDD - 0.8 VDD - 0.8 -- Typ(2) -- -- VDD - 0.4 VDD - 0.4 0.1 0.4 0.7VDD VSS -- -- -- -- -- -- -- -- -- -- -- 5.0 1.0 1.5 0.9 2 -- -- -- 0.2 80 -- -- -- -- -- -- 0.2 -- -- -- 12 22 1 5 12 8 -- -- Max -- 0.1 -- -- 0.4 1 VDD 0.2VDD 6 1.5 2 1 10 20 60 60 1 V V mA mA mA mA A A A A A A A A pF pF pF pF V Unit V
V
14
(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switching currents inherent in CMOS designs (see Section 2). (2) Typical values are at mid point of voltage range and at 25C only. (3) RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 4.2MHz); all inputs 0.2 V from rail; no DC loads; maximum load on outputs 50pF (20pF on OSC2). STOP /WAIT IDD: all ports configured as inputs; VIL = 0.2 V and VIH = VDD - 0.2 V: STOP IDD measured with OSC1 = VDD. WAIT IDD is affected linearly by the OSC2 capacitance.
Freescale E-22
MC68HC705B16
MC68HC05B6 Rev. 4.1
Table E-8 DC electrical characteristics for 3.3V operation
(VDD = 3.3Vdc 10%, VSS = 0Vdc, TA = TL to TH) Characteristic(1) Symbol Output voltage ILOAD = - 10 A VOH ILOAD = +10 A VOL Output high voltage (ILOAD = 0.8mA) VOH PA0-7, PB0-7, PC0-7, TCMP1, TCMP2 Output high voltage (ILOAD = 1.6mA) TDO, SCLK, PLMA, PLMB VOH Output low voltage (ILOAD = 1.6mA) PA0-7, PB0-7, PC0-7, TCMP1, TCMP2, VOL TDO, SCLK, PLMA, PLMB Output low voltage (ILOAD = 1.6mA) VOL RESET Input high voltage PA0-7, PB0-7, PC0-7, PD0-7, OSC1, VIH IRQ, RESET, TCAP1, TCAP2, RDI Input low voltage PA0-7, PB0-7, PC0-7, PD0-7, OSC1, IRQ, VIL RESET, TCAP1, TCAP2, RDI Supply current(3) IDD RUN (SM = 0) (See Figure 11-1) RUN (SM = 1) (See Figure 11-2) IDD WAIT (SM = 0) (See Figure 11-3) IDD WAIT (SM = 1) (See Figure 11-4) IDD STOP 0 to 70 (standard) IDD - 40 to 85 (extended) IDD - 40 to 105 (industrial) IDD - 40 to 125 (automotive) IDD High-Z leakage current PA0-7, PB0-7, PC0-7, TDO, RESET, SCLK IIL Input current Port B and port C pull-down (VIN =VIH) IRPD Input current (0 to 70) IRQ, OSC1, TCAP1, TCAP2, RDI, IIN PD0/AN0-PD7/AN7 (channel not selected) Input current (- 40 to 125) IIN IRQ, OSC1, TCAP1, TCAP2, RDI, PD0/AN0-PD7/AN7 (channel not selected) Capacitance Ports (as input or output), RESET, TDO, COUT SCLK CIN IRQ, TCAP1, TCAP2, OSC1, RDI CIN PD0/AN0-PD7/AN7 (A/D off) CIN PD0/AN0-PD7/AN7 (A/D on) Min VDD - 0.1 -- VDD - 0.3 VDD - 0.3 -- Typ(2) -- -- VDD - 0.1 VDD - 0.1 0.1 0.2 0.7VDD VSS -- -- -- -- -- -- -- -- -- -- Max -- 0.1 -- -- 0.4 0.6 VDD 0.2VDD 3 1 1.5 0.5 10 10 40 40 1 V Unit V
V
V
--
V
2.0 0.8 1.0 0.4 1 -- -- -- 0.2 80
mA mA mA mA A A A A A A
--
0.2
1
A
--
--
5
A
-- -- -- --
-- -- 12 22
12 8 -- --
pF pF pF pF
(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switching currents inherent in CMOS designs (see Section 2). (2) Typical values are at mid point of voltage range and at 25C only.
14
MC68HC05B6 Rev. 4.1 MC68HC705B16 Freescale E-23
(3) RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 2.0MHz); all inputs 0.2 V from rail; no DC loads; maximum load on outputs 50pF (20pF on OSC2). STOP /WAIT IDD: all ports configured as inputs; VIL = 0.2 V and VIH = VDD - 0.2 V: STOP IDD measured with OSC1 = VDD. WAIT IDD is affected linearly by the OSC2 capacitance.
14
Freescale E-24 MC68HC705B16 MC68HC05B6 Rev. 4.1
E.7
A/D converter characteristics
Table E-9 A/D characteristics for 5V operation
(VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH) Characteristic Resolution Non-linearity Parameter Number of bits resolved by the A/D Max deviation from the best straight line through the A/D transfer characteristics (VRH = VDD and VRL = 0V) Uncertainty due to converter resolution Difference between the actual input voltage and the full-scale equivalent of the binary code output code for all errors Analog input voltage range Maximum analog reference voltage Minimum analog reference voltage Minimum difference between VRH and VRL Total time to perform a single analog to digital conversion a. External clock (OSC1, OSC2) b. Internal RC oscillator Conversion result never decreases with an increase in input voltage and has no missing codes Conversion result when VIN = VRL Conversion result when VIN = VRH 00 -- -- -- -- -- Min 8 -- -- -- VRL VRL VSS - 0.1 3 -- -- Max -- 0.5 0.5 1 VRH VDD + 0.1 VRH -- 32 32 GUARANTEED -- FF 12 12 12 1 Hex Hex tCYC s pF A Unit Bit LSB LSB LSB V V V V tCYC s
Quantization error Absolute accuracy
Conversion range VRH VR(1) Conversion time VRL
Monotonicity Zero input reading Full scale reading
Sample acquisition time Analog input acquisition sampling a. External clock (OSC1, OSC2) b. Internal RC oscillator(2) Sample/hold capacitance Input capacitance on PD0/AN0-PD7/AN7 Input leakage(3) Input leakage on A/D pins PD0/AN0-PD7/AN7, VRL, VRH
(1) Performance verified down to 2.5V VR, but accuracy is tested and guaranteed at VR = 5V10%. (2) Source impedances greater than 10k will adversely affect internal charging time during input sampling. (3) The external system error caused by input leakage current is approximately equal to the product of R source and input current. Input current to A/D channel will be dependent on external source impedance (see Figure 8-2).
14
MC68HC05B6 Rev. 4.1 MC68HC705B16 Freescale E-25
Table E-10 A/D characteristics for 3.3V operation
(VDD = 3.3 Vdc 10%, VSS = 0 Vdc, TA = TL to TH) Characteristic Resolution Non-linearity Parameter Number of bits resolved by the A/D Max deviation from the best straight line through the A/D transfer characteristics (VRH = VDD and VRL = 0V) Uncertainty due to converter resolution Difference between the actual input voltage and the full-scale equivalent of the binary code output code for all errors Analog input voltage range Maximum analog reference voltage Minimum analog reference voltage Minimum difference between VRH and VRL Total time to perform a single analog to digital conversion Internal RC oscillator Conversion result never decreases with an increase in input voltage and has no missing codes Conversion result when VIN = VRL Conversion result when VIN = VRH 00 -- -- -- -- Min 8 -- -- -- VRL VRL VSS - 0.1 3 -- Max -- 1 1 2 VRH VDD + 0.1 VRH -- 32 GUARANTEED -- FF 12 12 1 Hex Hex s pF A Unit Bit LSB LSB LSB V V V V s
Quantization error Absolute accuracy
Conversion range VRH VRL VR Conversion time Monotonicity Zero input reading Full scale reading
Sample acquisition time Analog input acquisition sampling Internal RC oscillator(1) Sample/hold capacitance Input capacitance on PD0/AN0-PD7/AN7 Input leakage(2) Input leakage on A/D pins PD0/AN0-PD7/AN7, VRL, VRH
(1) Source impedances greater than 10k will adversely affect internal charging time during input sampling. (2) The external system error caused by input leakage current is approximately equal to the product of R source and input current. Input current to A/D channel will be dependent on external source impedance (see Figure 8-2).
14
Freescale E-26 MC68HC705B16 MC68HC05B6 Rev. 4.1
E.8
Control timing
Table E-11 Control timing for 5V operation
(VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH) Characteristic Symbol Frequency of operation Crystal option fOSC External clock option fOSC Internal operating frequency (fOSC/2) Using crystal fOP Using external clock fOP Cycle time (see Figure 9-1) tCYC Crystal oscillator start-up time (see Figure 9-1) tOXOV Stop recovery start-up time (crystal oscillator) tILCH RC oscillator stabilization time tADRC A/D converter stabilization time tADON External RESET input pulse width tRL Power-on RESET output pulse width 4064 cycle tPORL 16 cycle tPORL Watchdog RESET output pulse width tDOGL Watchdog time-out tDOG EEPROM byte erase time tERA 0 to 70 (standard) - 40 to 85 (extended) tERA - 40 to 105 (industrial) tERA - 40 to 125 (automotive) tERA EEPROM byte program time(1) tPROG 0 to 70 (standard) - 40 to 85 (extended) tPROG - 40 to 105 (industrial) tPROG - 40 to 125 (automotive) tPROG Timer (see Figure E-11) Resolution(2) tRESL Input capture pulse width tTH, tTL Input capture pulse period tTLTL Interrupt pulse width (edge-triggered) tILIH Interrupt pulse period tILIL OSC1 pulse width(5) tOH, tOL Write/Erase endurance(6)(7) -- -- Data retention(6)(7) Min -- dc dc dc 480 -- Max 4.2 4.2 2.1 2.1 -- 100 100 5 500 -- -- -- -- 7168 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit MHz MHz MHz MHz ns ms ms s s tCYC tCYC tCYC tCYC tCYC ms ms ms ms ms ms ms ms tCYC ns tCYC ns tCYC ns cycles years
1.5 4064 16 1.5 6144 10 10 10 10 10 10 15 20 4 125 --(3) 125 --(4) 90 10000 10
(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when programming the EEPROM. (2) Since a 2-bit prescaler in the timer must count four external cycles (tCYC), this is the limiting factor in determining the timer resolution. (3) The minimum period tTLTL should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 tCYC. (4) The minimum period tILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 tCYC. (5) tOH and tOL should not total less than 238ns. (6) At a temperature of 85C (7) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information.
14
Freescale E-27
MC68HC05B6 Rev. 4.1
MC68HC705B16
Table E-12 Control timing for 3.3V operation
(VDD = 3.3Vdc 10%, VSS = 0 Vdc, TA = TL to TH) Characteristic Frequency of operation Crystal option External clock option Internal operating frequency (fOSC/2) Using crystal Using external clock Cycle time (see Figure 9-1) Crystal oscillator start-up time (see Figure 9-1) Stop recovery start-up time (crystal oscillator) RC oscillator stabilization time A/D converter stabilization time External RESET input pulse width Power-on RESET output pulse width 4064 cycle 16 cycle Watchdog RESET output pulse width Watchdog time-out EEPROM byte erase time 0 to 70 (standard) - 40 to 85 (extended) - 40 to 105 (industrial) - 40 to 125 (automotive) EEPROM byte program time(1) 0 to 70 (standard) - 40 to 85 (extended) - 40 to 105 (industrial) - 40 to 125 (automotive) Timer (see Figure E-11) Resolution(2) Input capture pulse width Input capture pulse period Interrupt pulse width (edge-triggered) Interrupt pulse period OSC1 pulse width(5) Write/Erase endurance(6)(7) Data retention(6)(7) Symbol fOSC fOSC fOP fOP tCYC tOXOV tILCH tADRC tADON tRL tPORL tPORL tDOGL tDOG tERA tERA tERA tERA tPROG tPROG tPROG tPROG tRESL tTH, tTL tTLTL tILIH tILIL tOH, tOL -- -- 1.5 4064 16 1.5 6144 30 30 30 30 30 30 30 30 4 250 --(3) 250 --(4) 200 10000 10 Min -- dc -- dc 1000 -- Max 2.0 2.0 1.0 1.0 -- 100 100 5 500 -- -- -- -- 7168 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit MHz MHz MHz MHz ns ms ms s s tCYC tCYC tCYC tCYC tCYC ms ms ms ms ms ms ms ms tCYC ns tCYC ns tCYC ns cycles years
14
Freescale E-28
(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when programming the EEPROM. (2) Since a 2-bit prescaler in the timer must count four external cycles (tCYC), this is the limiting factor in determining the timer resolution. (3) The minimum period tTLTL should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 tCYC. (4) The minimum period tILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 tCYC. (5) tOH and tOL should not total less than 500ns. (6) At a temperature of 85C (7) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information.
MC68HC705B16
MC68HC05B6 Rev. 4.1
tTLTL External signal (TCAP1, TCAP2)
tTH
tTL
Figure E-11 Timer relationship
E.9
EPROM electrical characteristics
Table E-13 DC electrical characteristics for 5V operation
(VDD = 5 Vdc 10%, VSS = 0 Vdc, TA = 25C) Characteristic(1) EPROM Absolute maximum voltage Programming voltage Programming current Read voltage Symbol VPP6 max VPP6 IPP6 VPP6R Min VDD 15 -- VDD Typ(2) -- 15.5 50 VDD Max 18 16 64 VDD Unit V V mA V
(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switching currents inherent in CMOS designs (see Section 2). (2) Typical values are at mid point of voltage range and at 25C only.
Table E-14 Control timing for 5V operation
(VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = 25C) Characteristic EPROM programming time Symbol tPROG Min 5 Max 20 Unit ms
Table E-15 Control timing for 3.3V operation
(VDD = 3.3 Vdc 10%, VSS = 0 Vdc, TA = 25C) Characteristic EPROM programming time Symbol tPROG Min 5 Max 20 Unit ms
14
MC68HC05B6 Rev. 4.1 MC68HC705B16 Freescale E-29
14
Freescale E-30 MC68HC705B16 MC68HC05B6 Rev. 4.1
F
MC68HC705B16N
The MC68HC705B16N is a new device identical to the MC68HC705B16 in its memory map and functionality, except for the following: * * * * Bootloader Reset pulse width Reset twice issue Electrical characteristics
On the MC68HC705B16 there was a requirement to reset the device a second time after power-on. On the MC68HC705B16N this reset twice action is now not required. The interrupt service routine for the vector at address $3FF0-$3FF1 is no longer required, as the vector will never be fetched. However, the interrupt service routine and vector contents required for the MC68HC705B16 (see Section E, page E-1) can also be kept on the MC68HC705B16N with no detrimental effect, although they will never be used.
The MC68HC705B16N is a device similar to the MC68HC05B6, but with increased RAM and 15 kbytes of EPROM instead of 6 kbytes of ROM. In addition, the self-check routines available in the MC68HC05B6 are replaced by bootstrap firmware. The MC68HC705B16N is an OTPROM (one-time programmable ROM) version of the MC68HC05B16, meaning that once the application program has been loaded in the EPROM it can never be erased. The entire MC68HC05B6 data sheet applies to the MC68HC705B16N, with the exceptions outlined in this appendix.
14
MC68HC05B6 Rev. 4.1 MC68HC705B16N Freescale F-1
F.1
* * * * * *
Features
15 kbytes EPROM 352 bytes of RAM 576 bytes bootstrap ROM Simultaneous programming of up to 8 bytes of EPROM Optional pull-down resistors available on all port B and port C pins 52-pin PLCC and 64-pin QFP packages
VPP1
Charge pump
576 bytes bootstrap ROM
Port A
256 bytes EEPROM
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2/ECLK PC3 PC4 PC5 PC6 PC7 TCMP1 TCMP2 TCAP1 TCAP2 RDI SCLK TDO PLMA D/A PLMB D/A
VPP6
15168 bytes EPROM Port B
RESET IRQ OSC2 OSC1
COP watchdog
Oscillator
VDD VSS
M68HC05 CPU 16-bit timer Port D
PD0/AN0 PD1/AN1 PD2/AN2 PD3/AN3 PD4/AN4 PD5/AN5 PD6/AN6 PD7/AN7 VRH VRL
8-bit A/D converter
SCI
PLM
Figure F-1 MC68HC705B16N block diagram
Note:
14
Freescale F-2
The electrical characteristics of the MC68HC05B6 as provided in Section 11 do not apply to the MC68HC705B16N. Data specific to the MC68HC705B16N can be found in this appendix.
MC68HC705B16N
Port C
/ 2 / / 32
352 bytes static RAM
MC68HC05B6 Rev. 4.1
MC68HC705B16 $0000 I/O (32 bytes) $0020 Page 0 User EPROM (48 bytes)
Registers
Port A data register Port B data register Port C data register Port D input data register Port A data direction register Port B data direction register Port C data direction register E/EEPROM/ECLK control register $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F
$0050 RAM1 (176 bytes) Stack Options register Unprotected (31 bytes) EEPROM (256 bytes) Protected (224 bytes) $0200 $0250 $0300 $3DFE $3DFF $3E00 Bootstrap ROM1 (80 bytes) RAM11 (176 bytes) User EPROM (15104 bytes) Mask option register Bootstrap ROM11 (496 bytes) $3FF0-1 $3FF2-3 SCI Timer overflow $3FF4-5 $3FF6-7 Timer output compare 1& 2 $3FF8-9 Timer input capture 1 & 2 External IRQ $3FFA-B $3FFC-D SWI $3FFE-F Reset/power-on reset
A/D data register A/D status/control register Pulse length modulation A Pulse length modulation B Miscellaneous register SCI baud rate register SCI control register 1 SCI control register 2 SCI status register SCI data register Timer control register Timer status register Capture high register 1 Capture low register 1 Compare high register 1 Compare low register 1 Counter high register Counter low register Alternate counter high register Alternate counter low register Capture high register 2 Capture low register 2 Compare high register 2 Compare low register 2
$00C0 $0100 $0101 $0120
User vectors (14 bytes) Reserved
Options register Mask option register
$0100 $3DFE
Figure F-2 Memory map of the MC68HC705B16N
14
MC68HC05B6 Rev. 4.1 MC68HC705B16N Freescale F-3
Table F-1 Register outline
Register name Port A data (PORTA) Port B data (PORTB) Port C data (PORTC) Port D data (PORTD) Port A data direction (DDRA) Port B data direction (DDRB) Port C data direction (DDRC) EPROM/EEPROM/ECLK control A/D data (ADDATA) A/D status/control (ADSTAT) Pulse length modulation A (PLMA) Pulse length modulation B (PLMB) Miscellaneous SCI baud rate (BAUD) SCI control 1 (SCCR1) SCI control 2 (SCCR2) SCI status (SCSR) SCI data (SCDR) Timer control (TCR) Timer status (TSR) Input capture high 1 Input capture low 1 Output compare high 1 Output compare low 1 Timer counter high Timer counter low Alternate counter high Alternate counter low Input capture high 2 Input capture low 2 Output compare high 2 Output compare low 2 Options (OPTR)(3) Mask option register (MOR)(4) Address bit 7 $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C POR(1) INTP $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F $0100 $3DFE EE1P ICIE ICF1 OCIE OCF1 TOF ICF2 OCF2 SPC1 R8 TIE TDRE SPC0 T8 TCIE TC RIE RDRF INTN SCT1 INTE SCT0 M ILIE IDLE SFA SCT0 TE OR SFB SCR2 RE NF SM SCR1 RWU FE COCO ADRC ADON 0 CH3 CH2 CH1 CH0 PD7 PD6 PD5 PD4 PD3 PC2/ ECLK PD2 PD1 PD0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Undefined Undefined Undefined Undefined 0000 0000 0000 0000 0000 0000 E6LAT E6PGM ECLK E1ERA E1LAT E1PGM 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 WDOG(2) ?001 000? SCR0 00uu uuuu LBCL SBK Undefined 0000 0000 1100 000u 0000 0000 TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0 Undefined Undefined Undefined Undefined Undefined 1111 1111 1111 1100 1111 1111 1111 1100 Undefined Undefined Undefined Undefined SEC Not affected RTIM RWAT WWAT PBPD PCPD Not affected
WAKE CPOL CPHA
(1) This bit is set each time there is a power-on reset. (2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1=watchdog enabled, 0=watchdog disabled. (3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits. (4) This register is implemented in EPROM; therefore reset has no effect on the individual bits.
14
Freescale F-4
MC68HC705B16N
MC68HC05B6 Rev. 4.1
F.2
External clock
When using an external clock the OSC1 and OSC2 pins should be driven in antiphase (see Figure D-2). The tOXOV or tILCH specifications (see Section F.9) do not apply when using an external clock input. The equivalent specification of the external clock source should be used in lieu of tOXOV or tILCH.
F.3
RESET pin
When the oscillator is running in a stable condition, the MCU is reset when a logic zero is applied to the RESET input for a minimum period of 3.0 machine cycles (tCYC). For more information see Section 9.1.3.
F.4
EPROM
The MC68HC705B16N memory map is given in Figure F-2. The device has a total of 15168 bytes of EPROM (including 14 bytes for User vectors) and 256 bytes of EEPROM. The EPROM array is supplied by the VPP6 pin in both read and program modes. Typically the user's software would be loaded into a programming board where VPP6 is controlled by one of the bootstrap loader routines. It would then be placed in an application where no programming occurs. In this case the VPP6 pin should be hardwired to VDD. Warning: A minimum VDD voltage must be applied to the VPP6 pin at all times, including power-on. Failure to do so could result in permanent damage to the device. Unless otherwise stated, EPROM programming is guaranteed at ambient (25C) temperature only.
F.4.1
EPROM read operation
The execution of a program in the EPROM address range or a load from the EPROM are both read operations. The E6LAT bit in the EPROM/EEPROM control register should be cleared to `0' which automatically resets the E6PGM bit. In this way the EPROM is read like a normal ROM. Reading the EPROM with the E6LAT bit set will give data that does not correspond to the actual memory content. As interrupt vectors are in EPROM, they will not be loaded when E6LAT is set. Similarly, the bootstrap ROM routines cannot be executed when E6LAT is set. In read mode, the VPP6 pin must be at the VDD level. When entering the STOP mode, the EPROM is automatically set to the read mode. Note: An erased byte reads as $00.
14
Freescale F-5
MC68HC05B6 Rev. 4.1
MC68HC705B16N
F.4.2
EPROM program operation
Typically the EPROM will be programmed by the bootstrap routines resident in the on-chip ROM. However, the user program can be used to program some EPROM locations if the proper procedure is followed. In particular, the programming sequence must be running in RAM, as the EPROM will not be available for code execution while the E6LAT bit is set. The VPP6 switching must occur externally after the E6PGM bit is set, for example under control of a signal generated on a pin by the programming routine. Note: When the part becomes a PROM, only the cumulative programming of bits to logic `1' is possible if multiple programming is made on the same byte.
To allow simultaneous programming of up to eight bytes, these bytes must be in the same group of addresses which share the same most significant address bits; only the three least significant bits can change.
F.4.3
EPROM/EEPROM/ECLK control register
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset
EPROM/EEPROM/ECLK control
$0007
E6LAT E6PGM ECLK E1ERA E1LAT E1PGM 0000 0000
E6LAT -- EPROM programming latch enable bit 1 (set) - Address and up to eight data bytes can be latched into the EPROM for further programming providing the E6PGM bit is cleared. Data can be read from the EPROM or firmware ROM; the E6PGM bit is reset to zero when E6LAT is `0'.
0 (clear) -
STOP, power-on and external reset clear the E6LAT bit. Note: After the tERA1 erase time or tPROG1 programming time, the E6LAT bit has to be reset to zero in order to clear the E6PGM bit.
E6PGM -- EPROM program enable bit This bit is the EPROM program enable bit. It can be set to `1' to enable programming only after E6LAT is set and at least one byte is written to the EPROM. It is not possible to clear this bit using software but clearing E6LAT will always clear E6PGM.
14
Note:
The E6PGM bit can never be set while the E6LAT bit is at zero.
Freescale F-6
MC68HC705B16N
MC68HC05B6 Rev. 4.1
Table F-2 EPROM control bits description
E6LAT E6PGM 0 1 1 0 0 1 Description Read/execute in EPROM Ready to write address/data to EPROM programming in progress
ECLK See Section 4.3. E1ERA -- EEPROM erase/programming bit Providing the E1LAT and E1PGM bits are at logic one, this bit indicates whether the access to the EEPROM is for erasing or programming purposes. 1 (set) - An erase operation will take place. A programming operation will take place.
0 (clear) -
Once the program/erase EEPROM address has been selected, E1ERA cannot be changed. E1LAT -- EEPROM programming latch enable bit 1 (set) - Address and data can be latched into the EEPROM for further program or erase operations, providing the E1PGM bit is cleared. Data can be read from the EEPROM. The E1ERA bit and the E1PGM bit are reset to zero when E1LAT is `0'.
0 (clear) -
STOP, power-on and external reset clear the E1LAT bit. Note: After the tERA1 erase time or tPROG1 programming time, the E1LAT bit has to be reset to zero in order to clear the E1ERA bit and the E1PGM bit.
E1PGM -- EEPROM charge pump enable/disable 1 (set) - Internal charge pump generator switched on. Internal charge pump generator switched off.
0 (clear) -
When the charge pump generator is on, the resulting high voltage is applied to the EEPROM array. This bit cannot be set before the data is selected, and once this bit has been set it can only be cleared by clearing the E1LAT bit. A summary of the effects of setting/clearing bits 0, 1 and 2 of the control register are given in Table F-3. Note: The E1PGM and E1ERA bits are cleared when the E1LAT bit is at zero.
14
MC68HC05B6 Rev. 4.1 MC68HC705B16N Freescale F-7
Table F-3 EEPROM control bits description
E1ERA 0 0 0 1 1 E1LAT E1PGM 0 1 1 1 1 0 0 1 0 1 Read condition Ready to load address/data for program/erase Byte programming in progress Ready for byte erase (load address) Byte erase in progress Description
F.4.4
Mask option register
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset
Mask option register (MOR)(1)
$3DFE
RTIM RWAT WWAT PBPD PCPD Not affected
(1) This register is implemented in EPROM; therefore reset has no effect on the individual bits.
RTIM -- Reset time This bit can modify the time tPORL, where the RESET pin is kept low after a power-on reset. 1 (set) - tPORL = 16 cycles. tPORL = 4064 cycles.
0 (clear) -
RWAT -- Watchdog after reset This bit can modify the status of the watchdog counter after reset. Usually, the watchdog system is disabled after power-on or external reset but when this bit is set, it will be active immediately after the following resets (except in bootstrap mode). WWAT -- Watchdog during WAIT mode This bit can modify the status of the watchdog counter in WAIT mode. Normally, the watchdog system is disabled in WAIT mode but when this bit is set, the watchdog will be active in WAIT mode. PBPD -- Port B pull-down This bit, when programmed, connects a resistive pull-down on each pin of port B. This pull-down, RPD, is active on a given pin only while it is an input.
14
Freescale F-8 MC68HC705B16N MC68HC05B6 Rev. 4.1
PCPD -- Port C pull-down This bit, when programmed, connects a resistive pull-down on each pin of port C. This pull-down, RPD, is active on a given pin only while it is an input.
F.4.5
EEPROM options register (OPTR)
Address Options (OPTR)(1) $0100 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 EE1P bit 0 State on reset
SEC Not affected
(1) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.
EE1P - EEPROM protect bit In order to achieve a higher degree of protection, the EEPROM is effectively split into two parts, both working from the VPP1 charge pump. Part 1 of the EEPROM array (32 bytes from $0100 to $011F) cannot be protected; part 2 (224 bytes from $0120 to $01FF) is protected by the EE1P bit in the options register. 1 (set) - Part 2 of the EEPROM array is not protected; all 256 bytes of EEPROM can be accessed for any read, erase or programming operations. Part 2 of the EEPROM array is protected; any attempt to erase or program a location will be unsuccessful.
0 (clear) -
When this bit is set to 1 (erased), the protection will remain until the next power-on or external reset. EE1P can only be written to `0' when the E1LAT bit in the EEPROM control register is set. Note: The EEPROM1 protect function is disabled while in bootstrap mode.
SEC -- Secure bit This bit allows the EPROM and EEPROM1 to be secured from external access. When this bit is in the erased state (set), the EPROM and EEPROM1 content is not secured and the device may be used in non user mode. When the SEC bit is programmed to `zero', the EPROM and EEPROM1 content is secured by prohibiting entry to the non user mode. To deactivate the secure bit, the EPROM has to be erased by exposure to a high density ultraviolet light, and the device has to be entered into the EPROM erase verification mode with PD1 set. When the SEC bit is changed, its new value will have no effect until the next power-on or external reset. 1 (set) - EEPROM/EPROM not protected. EEPROM/EPROM protected.
0 (clear) -
14
Freescale F-9
MC68HC05B6 Rev. 4.1
MC68HC705B16N
F.5
Bootstrap mode
Oscillator divide-by-two is forced in bootstrap mode. The 432 bytes of self-check firmware on the MC68HC05B6 are replaced by 576 bytes of bootstrap firmware. A detailed description of the modes of operation within bootstrap mode is given below. The bootstrap program in mask ROM address locations $0200 to $024F and $3E00 to $3FEF can be used to program the EPROM and the EEPROM, to check if the EPROM is erased or to load and execute data in RAM. After reset, while going to the bootstrap mode, the vector located at address $3FEE and $3FEF (RESET) is fetched to start execution of the bootstrap program. To place the part in bootstrap mode, the IRQ pin should be at 2xVDD with the TCAP1 pin `high' during transition of the RESET pin from low to high. The hold time on the IRQ and TCAP1 pins is two clock cycles after the external RESET pin is brought high. When the MC68HC705B16N is placed in the bootstrap mode, the bootstrap reset vector will be fetched and the bootstrap firmware will start to execute. Table F-4 shows the conditions required to enter each level of bootstrap mode on the rising edge of RESET.
Table F-4 Mode of operation selection
IRQ pin VSS to VDD 2xVDD 2xVDD 2xVDD 2xVDD 2xVDD 2xVDD x = Don't care TCAP1 pin PD1 PD2 PD3 PD4 VSS to VDD VDD VDD VDD VDD VDD VDD x 0 0 1 1 1 x x 0 0 0 0 0 0 x 0 1 0 1 0 1 x 0 0 0 0 1 1 Single chip Erased EPROM verification EPROM verification; EPROM verification; erase EEPROM; EPROM/EEPROM parallel program/verify Erased EPROM verification; erase EEPROM; EPROM parallel program/verify (no E2) Jump to start of RAM ($0051); SEC bit = NON ACTIVE Serial RAM load/execute - similar to MC68HC05B6 but can fill RAM I and II Mode
The bootstrap program will first copy part of itself in RAM (except `RAM parallel load'), as the program cannot be executed in ROM during verification/programming of the EPROM. It will then set the TCMP1 output to a logic high level, unlike the MC68HC05B6 which keeps TCMP1 low. This can be used to distinguish between the two circuits and, in particular, for selection of the VPP level and current capability.
14
Freescale F-10 MC68HC705B16N MC68HC05B6 Rev. 4.1
Reset
IRQ at 2xVDD? Y TCAP1=VDD? Y PD4 set? N Non-user mode Y PD2 set? N PD3 set? Y PD1 set? N Red LED on Y SEC bit active? N
N
User mode Y
N
SEC bit active?
N
Non-user mode
Y
SEC bit active? N N PD2 set? N Y Erased EPROM verification PD3 set? N Jump to RAM ($0051) N
Y
Red LED on
Y
Non-user mode
Y
Serial RAM load/execute
EPROM verify
Verify EPROM
EPROM erased? Y
Red LED on
Erased EPROM verification
Red LED on
N
EPROM verified? Y
Green LED on Y PD1 set? Y D N
Green LED on
14
Figure F-3 Modes of operation flow chart (1 of 2) MC68HC05B6 Rev. 4.1 MC68HC705B16N Freescale F-11
D
EEPROM byte erase and verify N
EEPROM erased?
Y Parallel program and verify
PD3 set? Y Go to $300 (EPROM only)
N
Go to $100 (EPROM and EEPROM)
Parallel program
Data verified? Y
N
Red LED on Green LED on
14
Freescale F-12
Figure F-4 Modes of operation flow chart (2 of 2)
MC68HC705B16N
MC68HC05B6 Rev. 4.1
F.5.1
Erased EPROM verification
If a non $00 byte is detected, the red LED will be turned on and the routine will stop (see Figure F-3 and Figure F-4). Only when the whole EPROM content is verified as erased will the green LED be turned on. PD1 is then checked. If PD1=0, the bootstrap program stops here and no programming occurs until such time as a high level is sensed on PD1. If PD1 = 1, the bootstrap program proceeds to erase the EEPROM1 for a nominal 2.5 seconds (4.0 MHz crystal). It is then checked for complete erasure; if any EEPROM byte is not erased, the program will stop before erasing the SEC byte. When both EPROM and EEPROM1 are completely erased and the security bit is cleared the programming operation can be performed. A schematic diagram of the circuit required for erased EPROM verification is shown in Figure F-8.
F.5.2
EPROM/EEPROM parallel bootstrap
Within this mode there are various subsections which can be utilised by correctly configuring the port pins shown in Table F-4. The erased EPROM verification program will be executed first as described in Section F.5.1. The EPROM programming time is set to 10 milliseconds with the bootstrap program and verify for the EPROM taking approximately 15 seconds. The EPROM will be loaded in increasing address order with non EPROM segments being skipped by the loader. Simultaneous programming is performed by reading eight bytes of data before actual programming is performed, thus dividing the loading time of the internal EPROM by 8. If any block of 8 EPROM bytes or 1 EEPROM byte of data is in the erased state, no programming takes place, thus speeding up the execution time. Parallel data is entered through Port A, while the 15-bit address is output on port B, PC0 to PC4 and TCMP1 and TCMP2. If the data comes from an external EPROM, the handshake can be disabled by connecting together PC5 and PC6. If the data is supplied by a parallel interface, handshake will be provided by PC5 and PC6 according to the timing diagram of Figure F-6 (see also Figure F-7). During programming, the green LED will flash at about 3 Hz. Upon completion of the programming operation, the EPROM and EEPROM1 content will be checked against the external data source. If programming is verified the green LED will stay on, while an error will cause the red LED to be turned on. Figure F-7 is a schematic diagram of a circuit which can be used to program the EPROM or to load and execute data in the RAM. Note: The entire EPROM and EEPROM1 can be loaded from the external source; if it is desired to leave a segment undisturbed, the data for this segment should be all $00s for EPROM data and all $FFs for EEPROM1 data.
14
MC68HC05B6 Rev. 4.1 MC68HC705B16N Freescale F-13
Address
HDSK out (PC5) Data
HDSK in (PC6) F29
Data read
Data read
Figure F-5 Timing diagram with handshake
tCOOE Address tADE tDHE tADE
tCOOE
tCOOE
tCDDE
tDHE
tADE
tDHE
tADE
tDHE
Data tADE max (address to data delay) tDHA min (data hold time) tCOOE (load cycle time) tCDDE (programming cycle time) 5 machine cycles 14 machine cycles 117 machine cycles < tCOOE < 150 machine cycles tCOOE + tPROG (10 ms nominal for EPROM; 10ms for EEPROM1)) 1 machine cycle = 1/(2f0(Xtal))
Figure F-6 Parallel EPROM loader timing diagram
14
Freescale F-14 MC68HC705B16N MC68HC05B6 Rev. 4.1
P1
RESET 100k 1N914 1k 1.0F + RUN 1N914 100F +
1 2 3
GND +5V VPP
+
TCAP1 VRH VDD IRQ RESET OSC1 OSC2 RDI VRL TCAP2 PD7 PD6 PD5 PD3 PD2 PD1 PD0
4.0 MHz 22pF 22pF
47F
red LED 0.01F 470 470 Boot red LED -- programming failed green LED -- programming OK Erase check green LED -- EPROM erased red LED -- EPROM not erased green LED
NC TCMP1 VPP1 PLMA PLMB
EPROM verify Erase check & boot (EPROM only)
Erase verify & boot
Erase check & boot (EPROM & EEPROM)
EPROM check
+5V 1 27 28 VPP PGM VCC A14 26 A13 A0 A1 A2 A3 A4 20 CE A5 A6 27C256 A7 D0 D1 D2 D3 D4 D5 D6 D7 GND 14 OE 22 10 9 8 7 6 5 4 3 11 12 13 15 16 17 18 19
MC68HC705B16N MCU
EPROM 1N5819
PD4 SCLK TDO TCMP2 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 VSS
1 k BC309C
10k
VPP6
12 k 4k7
PC7
4k7
BC239C
1nF
+
+5V
100 k HDSK out Short circuit if handshake not used
25 24 21 23 2
PC5 PC6 PC4 PC3 PC2 PC1 PC0 A12 A11 A10 A9 A8
A8 A9 A10 A11 A12
HDSK in
Note:
This circuit is recommended for programming only at 25C and not for use in the end application, or at temperatures other than 25C. If used in the end application, VPP6 should be tied to VDD to avoid damaging the device.
14
Figure F-7 EPROM parallel bootstrap schematic diagram MC68HC05B6 Rev. 4.1 MC68HC705B16N Freescale F-15
F.5.3
Serial RAM loader
This mode is similar to the RAM load/execute program for the MC68HC05B6 described in Section 2.2, with the additional features listed below. Table F-4 shows the entry conditions required for this mode. If the first byte is less than $B0, the bootloader behaves exactly as the MC68HC05B6, i.e. count byte followed by data stored in $0050 to $00FF. If the count byte is larger than RAM I (176 bytes) then the code continues to fill RAM II. In this case the count byte is ignored and the program execution begins at $0051 once the total RAM area is filled or if no data is received for 5 milliseconds. The user must take care when using branches or jumps as his code will be relocated in RAM I and II. If the user intends to use the stack in his program, he should send NOP's to fill the desired stack area. In the RAM bootloader mode, all interrupt vectors are mapped to pseudo-vectors in RAM (see Table F-5). This allows programmers to use their own service-routine addresses. Each pseudo-vector is allowed three bytes of space rather than the two bytes for normal vectors, because an explicit jump (JMP) opcode is needed to cause the desired jump to the users service-routine address.
Table F-5 Bootstrap vector targets in RAM
Vector targets in RAM SCI interrupt Timer overflow Timer output compare Timer input capture IRQ SWI $0063 $0060 $005D $005A $0057 $0054
F.5.3.1
Jump to start of RAM ($0051)
The Jump to start of RAM program will be executed when the device is brought out of reset with PD1 and PD4 at `1' and PD2 and PD3 at `0'.
14
Freescale F-16 MC68HC705B16N MC68HC05B6 Rev. 4.1
P1
1 2 3
RESET 100k 1k
RUN 1N914 1.0F +
GND +5V VPP
10nF
+ 47F
22 19
8
10
1N914
TCAP1 VRH VDD IRQ OSC1
47F +
18 RESET
Red LED 0.01F 470 470 Green LED
20 21
PLMA PLMB
OSC2
4.0 MHz 22pF 22pF
PD3
Erase check Green LED -- EPROM erased Red LED -- EPROM not erased
RAM load & execute Jump to $51
MC68HC705B16N MCU (socket)
Serial boot
PD4
Serial boot Flashing green LED -- programming Green LED -- programming ended 1 k BC309C 1N5819 12 k 4k7
39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 14 13 12 5 4 3
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PD0 PD1 PD2 PD5 PD6 PD7
10k
VPP6
PC7
4k7
BC239C
1nF
+
Serial RAM load & execute
9600 BD 8-bit no parity
8 5 7 3 2 1 2 x 3K
22F + 2
+5V
16 1 3 4 5 12 11 + 22F + 22F
PC6 PC5 PC4 PC3 PC2 PC1 PC0
43 44 45 46 47 48 49
RS232 Connector
22F + 6 13 14
MAX 232
50 RDI 52 TDO VSS 41
15
VPP1 23 TCAP2 2 TCMP1 1 TCMP2 51 SCLK 40 NC VRL
7
Note:
A minimum VDD voltage must be applied to the VPP6 pin at all times, including power-on, as a lower voltage could damage the device. Unless otherwise stated, EPROM programming is guaranteed at ambient (25C) temperature only
14
Freescale F-17
Figure F-8 RAM load and execute schematic diagram
MC68HC05B6 Rev. 4.1
MC68HC705B16N
tCR
Address PC5 out tHO tADR tDHR
Data PC6 in tHI max
PD4
tEXR max
tADR max (address to data delay; PC6=PC5) tDHR min (data hold time) tCR (load cycle time; PC6=PC5) tHO (PC5 handshake out delay) tHI max (PC6 handshake in, data hold time) tEXR max (max delay for transition to be recognised during this cycle; PC6=PC5 1 machine cycle = 1/(2f0(Xtal))
16 machine cycles 4 machine cycles 49 machine cycles 5 machine cycles 10 machine cycles 30 machine cycles
Figure F-9 Parallel RAM loader timing diagram
14
Freescale F-18 MC68HC705B16N MC68HC05B6 Rev. 4.1
F.6
Absolute maximum ratings
Table F-6 Absolute maximum ratings
Rating Supply voltage(1) Input voltage (Except VPP1 and VPP6) Input voltage - Self-check mode (IRQ pin only) Operating temperature range - Standard (MC68HC705B16N) - Extended (MC68HC705B16NC) - Industrial (MC68HC705B16NV) - Automotive (MC68HC705B16NM) Storage temperature range Current drain per pin (excluding VDD and VSS)(2) - Source - Sink (1) All voltages are with respect to VSS. (2) Maximum current drain per pin is for one pin at a time, limited by an external resistor. Symbol VDD VIN VIN TA Value - 0.5 to +7.0 VSS - 0.5 to VDD + 0.5 VSS - 0.5 to 2VDD + 0.5 TL to TH 0 to +70 -40 to +85 -40 to +105 -40 to +125 - 65 to +150 25 45 Unit V V V
C
TSTG ID IS
C mA mA
Note:
This device contains circuitry designed to protect against damage due to high electrostatic voltages or electric fields. However, it is recommended that normal precautions be taken to avoid the application of any voltages higher than those given in the maximum ratings table to this high impedance circuit. For maximum reliability all unused inputs should be tied to either VSS or VDD.
14
MC68HC05B6 Rev. 4.1 MC68HC705B16N Freescale F-19
F.7
DC electrical characteristics
Table F-7 DC electrical characteristics for 5V operation
(VDD = 5 Vdc 10%, VSS = 0 Vdc, TA = TL to TH) Symbol Characteristic(1) Output voltage ILOAD = - 10 A VOH ILOAD = +10 A VOL Output high voltage (ILOAD = 0.8mA) PA0-7, PB0-7, PC0-7, TCMP1, TCMP2 VOH Output high voltage (ILOAD = 1.6mA) VOH TDO, SCLK, PLMA, PLMB Output low voltage (ILOAD = 1.6mA) PA0-7, PB0-7, PC0-7, TCMP1, TCMP2, VOL TDO, SCLK, PLMA, PLMB Output low voltage (ILOAD = 1.6mA) VOL RESET Input high voltage PA0-7, PB0-7, PC0-7, PD0-7, OSC1, VIH IRQ, RESET, TCAP1, TCAP2, RDI Input low voltage VIL PA0-7, PB0-7, PC0-7, PD0-7, OSC1, IRQ, RESET, TCAP1, TCAP2, RDI Supply current(3) RUN (SM = 0) (See Figure 11-1) IDD IDD RUN (SM = 1) (See Figure 11.2) IDD WAIT (SM = 0) (See Figure 11-3) IDD WAIT (SM = 1) (See Figure 11-4) STOP IDD 0 to 70 (standard) IDD - 40 to 85 (extended) IDD - 40 to 105 (industrial) IDD - 40 to 125 (automotive) High-Z leakage current IIL PA0-7, PB0-7, PC0-7, TDO, RESET, SCLK Input current Port B and port C pull-down (VIN =VIH) IRPD Input current (0 to 70) IIN IRQ, OSC1, TCAP1, TCAP2, RDI, PD0/AN0-PD7/AN7 (channel not selected) Input current (- 40 to 125) IIN IRQ, OSC1, TCAP1, TCAP2, RDI, PD0/AN0-PD7/AN7 (channel not selected) Capacitance Ports (as input or output), RESET, TDO, SCLK COUT CIN IRQ, TCAP1, TCAP2, OSC1, RDI CIN PD0/AN0-PD7/AN7 (A/D off) CIN PD0/AN0-PD7/AN7 (A/D on) Min VDD - 0.1 -- VDD - 0.8 VDD - 0.8 -- Typ(2) -- -- VDD - 0.4 VDD - 0.4 0.1 0.4 0.7VDD VSS -- -- -- -- -- -- -- -- -- -- -- 5.0 1.0 1.5 0.9 2 -- -- -- 0.2 80 -- -- -- -- -- -- 0.2 -- -- -- 12 22 1 5 12 8 -- -- Max -- 0.1 -- -- 0.4 1 VDD 0.2VDD 6 1.5 2 1 10 20 60 100 1 V V mA mA mA mA A A A A A A A A pF pF pF pF V Unit V
V
14
(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switching currents inherent in CMOS designs (see Section 2). (2) Typical values are at mid point of voltage range and at 25C only. (3) RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 4.2MHz); all inputs 0.2 V from rail; no DC loads; maximum load on outputs 50pF (20pF on OSC2). STOP /WAIT IDD: all ports configured as inputs; VIL = 0.2 V and VIH = VDD - 0.2 V: STOP IDD measured with OSC1 = VDD. WAIT IDD is affected linearly by the OSC2 capacitance.
Freescale F-20
MC68HC705B16N
MC68HC05B6 Rev. 4.1
Table F-8 DC electrical characteristics for 3.3V operation
(VDD = 3.3Vdc 10%, VSS = 0Vdc, TA = TL to TH) Characteristic(1) Symbol Output voltage ILOAD = - 10 A VOH ILOAD = +10 A VOL Output high voltage (ILOAD = 0.8mA) VOH PA0-7, PB0-7, PC0-7, TCMP1, TCMP2 Output high voltage (ILOAD = 1.6mA) TDO, SCLK, PLMA, PLMB VOH Output low voltage (ILOAD = 1.6mA) PA0-7, PB0-7, PC0-7, TCMP1, TCMP2, VOL TDO, SCLK, PLMA, PLMB Output low voltage (ILOAD = 1.6mA) VOL RESET Input high voltage PA0-7, PB0-7, PC0-7, PD0-7, OSC1, VIH IRQ, RESET, TCAP1, TCAP2, RDI Input low voltage PA0-7, PB0-7, PC0-7, PD0-7, OSC1, IRQ, VIL RESET, TCAP1, TCAP2, RDI Supply current(3) IDD RUN (SM = 0) (See Figure 11-1) RUN (SM = 1) (See Figure 11-2) IDD WAIT (SM = 0) (See Figure 11-3) IDD WAIT (SM = 1) (See Figure 11-4) IDD STOP 0 to 70 (standard) IDD - 40 to 85 (extended) IDD - 40 to 105 (industrial) IDD - 40 to 125 (automotive) IDD High-Z leakage current PA0-7, PB0-7, PC0-7, TDO, RESET, SCLK IIL Input current Port B and port C pull-down (VIN =VIH) IRPD Input current (0 to 70) IRQ, OSC1, TCAP1, TCAP2, RDI, IIN PD0/AN0-PD7/AN7 (channel not selected) Input current (- 40 to 125) IIN IRQ, OSC1, TCAP1, TCAP2, RDI, PD0/AN0-PD7/AN7 (channel not selected) Capacitance Ports (as input or output), RESET, TDO, COUT SCLK CIN IRQ, TCAP1, TCAP2, OSC1, RDI CIN PD0/AN0-PD7/AN7 (A/D off) CIN PD0/AN0-PD7/AN7 (A/D on) Min VDD - 0.1 -- VDD - 0.3 VDD - 0.3 -- Typ(2) -- -- VDD - 0.1 VDD - 0.1 0.1 0.2 0.7VDD VSS -- -- -- -- -- -- -- -- -- -- Max -- 0.1 -- -- 0.4 0.6 VDD 0.2VDD 3 1 1.5 0.5 10 10 40 60 1 V Unit V
V
V
--
V
2.0 0.8 1.0 0.4 1 -- -- -- 0.2 80
mA mA mA mA A A A A A A
--
0.2
1
A
--
--
5
A
-- -- -- --
-- -- 12 22
12 8 -- --
pF pF pF pF
(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switching currents inherent in CMOS designs (see Section 2). (2) Typical values are at mid point of voltage range and at 25C only.
14
MC68HC05B6 Rev. 4.1 MC68HC705B16N Freescale F-21
(3) RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 2.0MHz); all inputs 0.2 V from rail; no DC loads; maximum load on outputs 50pF (20pF on OSC2). STOP /WAIT IDD: all ports configured as inputs; VIL = 0.2 V and VIH = VDD - 0.2 V: STOP IDD measured with OSC1 = VDD. WAIT IDD is affected linearly by the OSC2 capacitance.
14
Freescale F-22 MC68HC705B16N MC68HC05B6 Rev. 4.1
F.8
A/D converter characteristics
Table F-9 A/D characteristics for 5V operation
(VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH) Characteristic Resolution Non-linearity Parameter Number of bits resolved by the A/D Max deviation from the best straight line through the A/D transfer characteristics (VRH = VDD and VRL = 0V) Uncertainty due to converter resolution Difference between the actual input voltage and the full-scale equivalent of the binary code output code for all errors Analog input voltage range Maximum analog reference voltage Minimum analog reference voltage Minimum difference between VRH and VRL Total time to perform a single analog to digital conversion a. External clock (OSC1, OSC2) b. Internal RC oscillator Conversion result never decreases with an increase in input voltage and has no missing codes Conversion result when VIN = VRL Conversion result when VIN = VRH 00 -- -- -- -- -- Min 8 -- -- -- VRL VRL VSS - 0.1 3 -- -- Max -- 0.5 0.5 1 VRH VDD + 0.1 VRH -- 32 32 GUARANTEED -- FF 12 12 12 1 Hex Hex tCYC s pF A Unit Bit LSB LSB LSB V V V V tCYC s
Quantization error Absolute accuracy
Conversion range VRH VR(1) Conversion time VRL
Monotonicity Zero input reading Full scale reading
Sample acquisition time Analog input acquisition sampling a. External clock (OSC1, OSC2) b. Internal RC oscillator(2) Sample/hold capacitance Input capacitance on PD0/AN0-PD7/AN7 Input leakage(3) Input leakage on A/D pins PD0/AN0-PD7/AN7, VRL, VRH
(1) Performance verified down to 2.5V VR, but accuracy is tested and guaranteed at VR = 5V10%. (2) Source impedances greater than 10k will adversely affect internal charging time during input sampling. (3) The external system error caused by input leakage current is approximately equal to the product of R source and input current. Input current to A/D channel will be dependent on external source impedance (see Figure 8-2).
14
MC68HC05B6 Rev. 4.1 MC68HC705B16N Freescale F-23
Table F-10 A/D characteristics for 3.3V operation
(VDD = 3.3 Vdc 10%, VSS = 0 Vdc, TA = TL to TH) Characteristic Resolution Non-linearity Parameter Number of bits resolved by the A/D Max deviation from the best straight line through the A/D transfer characteristics (VRH = VDD and VRL = 0V) Uncertainty due to converter resolution Difference between the actual input voltage and the full-scale equivalent of the binary code output code for all errors Analog input voltage range Maximum analog reference voltage Minimum analog reference voltage Minimum difference between VRH and VRL Total time to perform a single analog to digital conversion Internal RC oscillator Conversion result never decreases with an increase in input voltage and has no missing codes Conversion result when VIN = VRL Conversion result when VIN = VRH 00 -- -- -- -- Min 8 -- -- -- VRL VRL VSS - 0.1 3 -- Max -- 1 1 2 VRH VDD + 0.1 VRH -- 32 GUARANTEED -- FF 12 12 1 Hex Hex s pF A Unit Bit LSB LSB LSB V V V V s
Quantization error Absolute accuracy
Conversion range VRH VRL VR Conversion time Monotonicity Zero input reading Full scale reading
Sample acquisition time Analog input acquisition sampling Internal RC oscillator(1) Sample/hold capacitance Input capacitance on PD0/AN0-PD7/AN7 Input leakage(2) Input leakage on A/D pins PD0/AN0-PD7/AN7, VRL, VRH
(1) Source impedances greater than 10k will adversely affect internal charging time during input sampling. (2) The external system error caused by input leakage current is approximately equal to the product of R source and input current. Input current to A/D channel will be dependent on external source impedance (see Figure 8-2).
14
Freescale F-24 MC68HC705B16N MC68HC05B6 Rev. 4.1
F.9
Control timing
Table F-11 Control timing for 5V operation
(VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH) Characteristic Symbol Frequency of operation Crystal option fOSC External clock option fOSC Internal operating frequency (fOSC/2) Using crystal fOP Using external clock fOP Cycle time (see Figure 9-1) tCYC Crystal oscillator start-up time (see Figure 9-1) tOXOV Stop recovery start-up time (crystal oscillator) tILCH RC oscillator stabilization time tADRC A/D converter stabilization time tADON External RESET input pulse width tRL Power-on RESET output pulse width 4064 cycle tPORL 16 cycle tPORL Watchdog RESET output pulse width tDOGL Watchdog time-out tDOG EEPROM byte erase time tERA 0 to 70 (standard) - 40 to 85 (extended) tERA - 40 to 105 (industrial) tERA - 40 to 125 (automotive) tERA EEPROM byte program time(1) tPROG 0 to 70 (standard) - 40 to 85 (extended) tPROG - 40 to 105 (industrial) tPROG - 40 to 125 (automotive) tPROG Timer (see Figure F-10) Resolution(2) tRESL Input capture pulse width tTH, tTL Input capture pulse period tTLTL Interrupt pulse width (edge-triggered) tILIH Interrupt pulse period tILIL OSC1 pulse width(5) tOH, tOL Write/Erase endurance(6) -- -- Data retention(6)(7) Min -- dc dc dc 480 -- Max 4.2 4.2 2.1 2.1 -- 100 100 5 500 -- -- -- -- 7168 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit MHz MHz MHz MHz ns ms ms s s tCYC tCYC tCYC tCYC tCYC ms ms ms ms ms ms ms ms tCYC ns tCYC ns tCYC ns cycles years
3.0 4064 16 1.5 6144 10 10 10 10 10 10 15 20 4 125 --(3) 125 --(4) 90 10000 10
(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when programming the EEPROM. (2) Since a 2-bit prescaler in the timer must count four external cycles (tCYC), this is the limiting factor in determining the timer resolution. (3) The minimum period tTLTL should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 tCYC. (4) The minimum period tILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 tCYC. (5) tOH and tOL should not total less than 238ns. (6) At a temperature of 85C (7) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information.
14
Freescale F-25
MC68HC05B6 Rev. 4.1
MC68HC705B16N
Table F-12 Control timing for 3.3V operation
(VDD = 3.3Vdc 10%, VSS = 0 Vdc, TA = TL to TH) Characteristic Frequency of operation Crystal option External clock option Internal operating frequency (fOSC/2) Using crystal Using external clock Cycle time (see Figure 9-1) Crystal oscillator start-up time (see Figure 9-1) Stop recovery start-up time (crystal oscillator) RC oscillator stabilization time A/D converter stabilization time External RESET input pulse width Power-on RESET output pulse width 4064 cycle 16 cycle Watchdog RESET output pulse width Watchdog time-out EEPROM byte erase time 0 to 70 (standard) - 40 to 85 (extended) - 40 to 105 (industrial) - 40 to 125 (automotive) EEPROM byte program time(1) 0 to 70 (standard) - 40 to 85 (extended) - 40 to 105 (industrial) - 40 to 125 (automotive) Timer (see Figure F-10) Resolution(2) Input capture pulse width Input capture pulse period Interrupt pulse width (edge-triggered) Interrupt pulse period OSC1 pulse width(5) Write/Erase endurance(6)(7) Data retention(6)(7) Symbol fOSC fOSC fOP fOP tCYC tOXOV tILCH tADRC tADON tRL tPORL tPORL tDOGL tDOG tERA tERA tERA tERA tPROG tPROG tPROG tPROG tRESL tTH, tTL tTLTL tILIH tILIL tOH, tOL -- -- 3.0 4064 16 1.5 6144 30 30 30 30 30 30 30 30 4 250 --(3) 250 --(4) 200 10000 10 Min -- dc -- dc 1000 -- Max 2.0 2.0 1.0 1.0 -- 100 100 5 500 -- -- -- -- 7168 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit MHz MHz MHz MHz ns ms ms s s tCYC tCYC tCYC tCYC tCYC ms ms ms ms ms ms ms ms tCYC ns tCYC ns tCYC ns cycles years
14
Freescale F-26
(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when programming the EEPROM. (2) Since a 2-bit prescaler in the timer must count four external cycles (tCYC), this is the limiting factor in determining the timer resolution. (3) The minimum period tTLTL should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 tCYC. (4) The minimum period tILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 tCYC. (5) tOH and tOL should not total less than 500ns. (6) At a temperature of 85C (7) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information.
MC68HC705B16N
MC68HC05B6 Rev. 4.1
tTLTL External signal (TCAP1, TCAP2)
tTH
tTL
Figure F-10 Timer relationship
F.10
EPROM electrical characteristics
Table F-13 DC electrical characteristics for 5V operation
(VDD = 5 Vdc 10%, VSS = 0 Vdc, TA = 25C) Characteristic(1) EPROM Absolute maximum voltage Programming voltage Programming current Read voltage Symbol VPP6 max VPP6 IPP6 VPP6R Min VDD 15 -- VDD Typ(2) -- 15.5 50 VDD Max 18 16 64 VDD Unit V V mA V
(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switching currents inherent in CMOS designs (see Section 2). (2) Typical values are at mid point of voltage range and at 25C only.
Table F-14 Control timing for 5V operation
(VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = 25C) Characteristic EPROM programming time Symbol tPROG Min 5 Max 20 Unit ms
Table F-15 Control timing for 3.3V operation
(VDD = 3.3 Vdc 10%, VSS = 0 Vdc, TA = 25C) Characteristic EPROM programming time Symbol tPROG Min 5 Max 20 Unit ms
14
MC68HC05B6 Rev. 4.1 MC68HC705B16N Freescale F-27
14
Freescale F-28 MC68HC705B16N MC68HC05B6 Rev. 4.1
G
MC68HC05B32
The MC68HC05B32 is a device similar to the MC68HC05B6, but with increased RAM and ROM sizes. The entire MC68HC05B6 data sheet applies to the MC68HC05B32, with the exceptions outlined in this appendix.
G.1
* * * * * *
Features
31248 bytes User ROM No page zero ROM 528 bytes of RAM 52-pin PLCC and 64-pin QFP packages for -40 to +85C operating temperature range (extended) 56-pin SDIP package for 0 to 70C operating temperature range High speed version not available Preliminary electrical specifications for the MC68HC05B32 should be taken as being similar to those for the MC68HC705B32. When silicon is fully available, the part will be re-characterised and new data made available.
Note:
G.2
External clock
When using an external clock the OSC1 and OSC2 pins should be driven in antiphase (see Figure D-2). The tOXOV or tILCH specifications (see Section H.9) do not apply when using an external clock input. The equivalent specification of the external clock source should be used in lieu of tOXOV or tILCH.
14
MC68HC05B6 Rev. 4.1 MC68HC05B32 Freescale G-1
VPP1
Charge pump
638 bytes self-check ROM
Port A
256 bytes EEPROM
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2/ECLK PC3 PC4 PC5 PC6 PC7 TCMP1 TCMP2 TCAP1 TCAP2 RDI SCLK TDO PLMA D/A PLMB D/A
VPP6
32 kbytes ROM Port B
RESET IRQ OSC2 OSC1
COP watchdog
Oscillator
VDD VSS
M68HC05 CPU 16-bit timer Port D
PD0/AN0 PD1/AN1 PD2/AN2 PD3/AN3 PD4/AN4 PD5/AN5 PD6/AN6 PD7/AN7 VRH VRL
8-bit A/D converter
SCI
PLM
Figure G-1 MC68HC05B32 block diagram
14
Freescale G-2 MC68HC05B32 MC68HC05B6 Rev. 4.1
Port C
/ 2 / /32
528 bytes static RAM
MC68HC05B32 $0000 I/O (32 bytes) $0020
Registers
Port A data register Port B data register Port C data register Port D input data register Port A data direction register Port B data direction register $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F
$0050 RAMI (176 bytes) Stack Options register Unprotected (31 bytes) EEPROM (256 bytes) Protected (224 bytes) $0200 $0250 $03B0 $0400 Bootloader ROMI (80 bytes) RAMII (352 bytes) Bootloader ROMII (80 bytes) User ROM (31232 bytes) Bootloader ROMIII (478 bytes)
Port C data direction register EEPROM/ECLK control register A/D data register A/D status/control register Pulse length modulation A Pulse length modulation B Miscellaneous register SCI baud rate register SCI control register 1 SCI control register 2 SCI status register SCI data register Timer control register Timer status register Capture high register 1 Capture low register 1 Compare high register 1 Compare low register 1 Counter high register Counter low register Alternate counter high register Alternate counter low register Capture high register 2 Capture low register 2 Compare high register 2 Compare low register 2
$00C0 $0100 $0101 $0120
$7E00 $7FDE $7FE0 $7FF0
Bootloader ROM vectors (16 bytes)
$7FF2-3 SCI Timer overflow $7FF4-5 $7FF6-7 Timer output compare 1& 2 $7FF8-9 Timer input capture 1 & 2 External IRQ $7FFA-B $7FFC-D SWI $7FFE-F Reset/power-on reset
Options register
$0100
User vectors (14 bytes) Reserved
Figure G-2 Memory map of the MC68HC05B32
14
MC68HC05B6 Rev. 4.1 MC68HC05B32 Freescale G-3
Table G-1 Register outline
Register name Port A data (PORTA) Port B data (PORTB) Port C data (PORTC) Port D data (PORTD) Port A data direction (DDRA) Port B data direction (DDRB) Port C data direction (DDRC) EEPROM/ECLK control A/D data (ADDATA) A/D status/control (ADSTAT) Pulse length modulation A (PLMA) Pulse length modulation B (PLMB) Miscellaneous SCI baud rate (BAUD) SCI control 1 (SCCR1) SCI control 2 (SCCR2) SCI status (SCSR) SCI data (SCDR) Timer control (TCR) Timer status (TSR) Input capture high 1 Input capture low 1 Output compare high 1 Output compare low 1 Timer counter high Timer counter low Alternate counter high Alternate counter low Input capture high 2 Input capture low 2 Output compare high 2 Output compare low 2 Options (OPTR)(3) Mask option register (MOR)(4) Address bit 7 $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C POR(1) INTP $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F $0100 $7FDE EE1P ICIE ICF1 OCIE OCF1 TOF ICF2 OCF2 SPC1 R8 TIE TDRE SPC0 T8 TCIE TC RIE RDRF INTN SCT1 INTE SCT0 M ILIE IDLE SFA SCT0 TE OR SFB SCR2 RE NF SM SCR1 RWU FE COCO ADRC ADON 0 CH3 CH2 CH1 CH0 0 0 0 0 PD7 PD6 PD5 PD4 PD3 PC2/ ECLK PD2 PD1 PD0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Undefined Undefined Undefined Undefined 0000 0000 0000 0000 0000 0000 ECLK E1ERA E1LAT E1PGM 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 WDOG(2) ?001 000? SCR0 00uu uuuu LBCL SBK Undefined 0000 0000 1100 000u 0000 0000 TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0 Undefined Undefined Undefined Undefined Undefined 1111 1111 1111 1100 1111 1111 1111 1100 Undefined Undefined Undefined Undefined SEC Not affected RTIM RWAT WWAT PBPD PCPD Not affected
WAKE CPOL CPHA
(1) This bit is set each time there is a power-on reset. (2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1 = watchdog enabled, 0 = watchdog disabled. (3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits. (4) This register is implemented in ROM; therefore reset has no effect on the individual bits.
14
Freescale G-4 MC68HC05B32 MC68HC05B6 Rev. 4.1
MC68HC705B32
Maskset errata
This errata section outlines the differences between two previously available masksets (D59J and D40J) and all other masksets. Unless otherwise stated, the main body of Appendix G refers to all these other masksets with any differences being noted in this errata section. * * * For the D59J and D40J masksets, the MCU only requires that a logic zero is applied to the RESET input for 1.5 tCYC. For D59J, 16 cycle POR delay option (tPORL) is not available
r P
ry H ina lim e ry a in
For the D59J maskset, oscillator divide ratio DIV10 is forced in Bootstrap mode. On all other revisions DIV2 is forced.
For the D59J:
The STOP Idd is greater than the expected value of 120A at 5 volts Vdd at a temperature of 20C with the CAN module enabled and in SLEEP mode. Typically the STOP Idd is in the region of 2.0 milliamps at 20C. The fault lies with the design of the EPROM array. When the STOP instruction is executed, the next opcode in memory is present on the data bus. A fault in the EPROM write data latch circuitry causes a latch to be driven to logic 0 on both sides when the data bus for that bit is logic 1. This results in increasing STOP Idd of 450A per data bus bit set to a logic 1. If all data bus bits are set to logic 1 (i.e. next opcode is $FF, STX 0,X) the STOP Idd shall be in the region of 3.6mA. The minimum STOP Idd is achieved by ensuring the opcode immediately following the STOP instruction is data $00. This corresponds to BRSET 0,ADDRESS,LABEL. If the label points to the next sequential instruction in memory then this has the effect of a 5 cycle NOP but note that the carry bit in the condition code register may be altered by the BRSET instruction.
P
lim re
P
lim re
ry a in
14
Freescale H-1
MC68HC05B6 Rev. 4.1
MC68HC705B32
Example STOP BRSET 0,$00,NEXT NEXT any CPU instruction
The address compared may be any address in the page zero memory and the only restriction is that it should not be a register with flags cleared by reading the register. The example shows the address compared to be port A data register and this should not cause any problems in any applications. High STOP Idd will be variable dependant upon the opcode following the STOP instruction. The more bits set in the following opcode, the higher the STOP Idd. The work around described above may be used on any 68HC05B32 or corrected version of the 68HC705B32 without problem. It simply adds a 5 cycle delay to the recovery from STOP and 3 bytes of additional code per STOP instruction but may alter the state of the carry bit in the CCR. Also for the D59J:
lim re P lim re P
ry a in ry a in
The EEPROM programming circuit only fully supports 16-byte simultaneous programming mode and does not support single byte programming correctly. The fault lies with the design of the EPROM array. A fault in the EPROM write data latch circuitry causes a latch to be driven to logic 0 on both sides when the data bus for that bit is logic 1. When the ELAT signal is removed, there is a race condition with the EPBS signal which results in the data bus value being copied to all the EPROM latches. Since 16-byte simultaneous programming functions correctly, it is a relatively simple matter to emulate single byte programming by first initialising all 16 data latches to $00 and then writing the data to be written to the appropriate address. This problem does not affect user application software in normally circumstances since it only applies to programming the EPROM array. The serial programming software should always simulate 16-byte programming. The Freescale software for programming the 705B32 from an IBM compatible PC functions in 16 byte programming mode. This program therefore correctly programs the EPROM. In normal circumstances this errata does not affect the user application software. This only affects software that programs the EPROM array. The parallel programming bootloader software within the 705B32 ROM performs 16-byte programming and so functions correctly.
14
Freescale H-2
lim re P
ry a in
MC68HC705B32
MC68HC05B6 Rev. 4.1
The MC68HC705B32 is an EPROM version of the MC68HC05B32, with the ROM replaced by a similar amount of EPROM. The entire MC68HC05B6 data sheet applies to the MC68HC705B32, with the exceptions outlined in this appendix.
H.1
* * * * * * * *
Features
31246 bytes user EPROM
No page zero EPROM at $20-$4F 528 bytes of RAM
638 bytes bootstrap ROM instead of 432 bytes of self-check ROM Simultaneous programming of EPROM with up to 16 bytes of different data -40 to +85C operating temperature range (extended) 52-pin PLCC, 56-pin SDIP and 64-pin QFP packages High speed version not available
P
lim re
ry a in
Note:
The electrical characteristics from the MC68HC05B6 data sheet should not be used for the MC68HC705B32. Data specific to this device can be found in Section H.7 and Section H.9.
P
lim re
ry a in
P
MC68HC05B6 Rev. 4.1
lim re
ry a in
14
Freescale H-3
MC68HC705B32
VPP1
Charge pump
638 bytes bootstrap ROM
Port A
256 bytes EEPROM
VPP6
RESET IRQ OSC2 OSC1
VDD VSS
M68HC05 CPU 16-bit timer Port D
PD0/AN0 PD1/AN1 PD2/AN2 PD3/AN3 PD4/AN4 PD5/AN5 PD6/AN6 PD7/AN7 VRH VRL
lim re P
8-bit A/D converter
ry a in
SCI PLM
Port C
lim re P
COP watchdog Oscillator
32 kbytes EPROM
Port B
ry a in
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7
/ 2 / /32
528 bytes static RAM
PC0 PC1 PC2/ECLK PC3 PC4 PC5 PC6 PC7 TCMP1 TCMP2 TCAP1 TCAP2 RDI SCLK TDO PLMA D/A PLMB D/A
Figure H-1 MC68HC705B32 block diagram
14
Freescale H-4
lim re P
ry a in
MC68HC05B6 Rev. 4.1
MC68HC705B32
MC68HC705B32 $0000 I/O (32 bytes) $0020
Registers
$0050 RAM1 (176 bytes) Stack
$00C0 $0100 $0101 $0120
Options register
Unprotected (31 bytes) EEPROM (256 bytes) Protected (224 bytes) Bootstrap ROMI (80 bytes) RAM11 (352 bytes) Bootstrap ROMII (80 bytes) User EPROM (31232 bytes)
r P r P
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Port A data register
$0000 $0001 $0002 $0003 $0004 $0005 $0006
Port B data register
Port C data register
Port D input data register
Port A data direction register
Port B data direction register
Port C data direction register
E/EEPROM/ECLK control register $0007 $0008 A/D data register A/D status/control register Pulse length modulation A Pulse length modulation B Miscellaneous register SCI baud rate register SCI control register 1 SCI control register 2 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F
$0200 $0250 $03B0 $0400
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Reserved
SCI status register SCI data register
Timer control register Timer status register
Capture high register 1 Capture low register 1
Compare high register 1 Compare low register 1 Counter high register Counter low register
Alternate counter high register Alternate counter low register Capture high register 2 Capture low register 2 Compare high register 2 Compare low register 2
$7E00 $7FDE $7FDF $7FE0 $7FF0-1
Bootstrap ROMIII (478 bytes) Mask option register
Bootstrap ROM vectors (16 bytes)
$7FF2-3 SCI Timer overflow $7FF4-5 $7FF6-7 Timer output compare 1& 2 $7FF8-9 Timer input capture 1 & 2 External IRQ $7FFA-B $7FFC-D SWI $7FFE-F Reset/power-on reset
Options register
$0100 $7FDE
Mask option register
User vectors (14 bytes)
Figure H-2 Memory map of the MC68HC705B32
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14
Freescale H-5
MC68HC05B6 Rev. 4.1
MC68HC705B32
Table H-1 Register outline
Register name Port A data (PORTA) Port B data (PORTB) Port C data (PORTC) Port D data (PORTD) Address bit 7 $0000 $0001 $0002 bit 6 bit 5
Port A data direction (DDRA) Port B data direction (DDRB)
Port C data direction (DDRC) A/D data (ADDATA)
EPROM/EEPROM/ECLK control A/D status/control (ADSTAT)
Pulse length modulation A (PLMA) Pulse length modulation B (PLMB) Miscellaneous SCI baud rate (BAUD) SCI control 1 (SCCR1) SCI control 2 (SCCR2) SCI status (SCSR) SCI data (SCDR) Timer control (TCR) Timer status (TSR) Input capture high 1 Input capture low 1 Output compare high 1 Output compare low 1 Timer counter high Timer counter low Alternate counter high Alternate counter low Input capture high 2 Input capture low 2 Output compare high 2 Output compare low 2 Options (OPTR)(3) Mask option register (MOR)(4)
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$0003 PD7 PD6 $0004 $0005 $0006 $0007 0 $0008 $0009 $000A $000B $000C POR(1) INTP $000D $000E $000F $0010 $0011 $0012 SPC1 R8 TIE TDRE ICIE SPC0 T8 TCIE TC OCIE
PD5
ry a in
PC2/ ECLK PD2 PD4 PD3 0 CH3 CH2
bit 4
bit 3
bit 2
bit 1
bit 0
State on reset Undefined Undefined Undefined
PD1
PD0
Undefined 0000 0000 0000 0000 0000 0000 0000 0000
E6LAT E6PGM ECLK E1ERA E1LAT E1PGM u000 0000 CH1 CH0 0000 0000 0000 0000 0000 0000 INTN SCT1 RIE INTE M SFA SFB SM WDOG(2) ?001 000? SCR0 00uu uuuu LBCL SBK Undefined 0000 0000 1100 000u 0000 0000 Undefined Undefined Undefined Undefined Undefined 1111 1111 1111 1100 1111 1111 1111 1100 Undefined Undefined Undefined Undefined SEC Not affected
COCO ADRC ADON
RDRF
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$0013 ICF1 OCF1 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F $0100 $7FDE
TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0 TOF ICF2 OCF2
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SCT0 ILIE SCT0 TE SCR2 RE NF IDLE OR
SCR1 RWU FE
WAKE CPOL CPHA
(1) This bit is set each time there is a power-on reset.
(2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1=watchdog enabled, 0=watchdog disabled. (3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits. (4) This register is implemented in EPROM; therefore reset has no effect on the individual bits.
14
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EE1P
RTIM RWAT WWAT PBPD PCPD Not affected
Freescale H-6
MC68HC705B32
MC68HC05B6 Rev. 4.1
H.2
External clock
When using an external clock the OSC1 and OSC2 pins should be driven in antiphase (see Figure D-2). The tOXOV or tILCH specifications (see Section H.9) do not apply when using an external clock input. The equivalent specification of the external clock source should be used in lieu of tOXOV or tILCH.
H.3
RESET pin
When the oscillator is running in a stable condition, the MCU is reset when a logic zero is applied to the RESET input for a minimum period of 3.0 machine cycles (tCYC). This differs from the 05B6, 05B4, 705B5, 05B8, 05B16, 705B16 and the 05B32, which require 1.5 tCYC. For more information see Section 9.1.3.
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H.4
EPROM
The MC68HC705B32 memory map is given in Figure H-2. The device has a total of 31246 bytes of EPROM. 14 bytes are used for the reset and interrupt vectors from address $7FF2 to $7FFF. The main EPROM block of 31232 bytes is located from $0400 to $7DFF. One byte of EPROM is used as an options register and is located at address $7FDE. The EPROM array is supplied by the VPP6 pin in both read and program modes. Typically the user's software will be loaded into a programming board where VPP6 is controlled by one of the bootstrap loader routines. It will then be placed in an application where no programming occurs. In this case the VPP6 pin should be hardwired to VDD.
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Warning: A minimum VDD voltage must be applied to the VPP6 pin at all times, including power-on. Failure to do so could result in permanent damage to the device. Unless otherwise stated, EPROM programming is guaranteed at ambient (25C) temperature only.
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MC68HC05B6 Rev. 4.1
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14
Freescale H-7
MC68HC705B32
H.4.1
EPROM read operation
The execution of a program in the EPROM address range or a load from the EPROM are both read operations. The E6LAT bit in the EPROM/EEPROM control register should be cleared to `0' which automatically resets the E6PGM bit. In this way the EPROM is read like a normal ROM. Reading the EPROM with the E6LAT bit set will give data that does not correspond to the actual memory content. As interrupt vectors are in EPROM, they will not be loaded when E6LAT is set. Similarly, the bootstrap ROM routines cannot be executed when E6LAT is set. In read mode, the VPP6 pin must be at the VDD level. When entering the STOP mode, the EPROM is automatically set to the read mode. Note: An erased byte reads as $00.
lim re P lim re P
Address bit 7 bit 6 0 $0007
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H.4.2
EPROM program operation
Typically, the EPROM will be programmed by the bootstrap routines resident in the on-chip ROM. However, the user program can be used to program some EPROM locations if the proper procedure is followed. In particular, the programming sequence must be running in RAM, as the EPROM will not be available for code execution while the E6LAT bit is set. The VPP6 switching must occur externally after EPGM is set, for example under control of a signal generated on a pin by the programming routine. Note: Unless the part has a window for reprogramming, only the cumulative programming of bits to logic `1' is possible if multiple programming is made on the same byte.
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bit 4 bit 3 bit 2
To allow simultaneous programming of up to sixteen bytes, these bytes must be in the same group of addresses which share the same most significant address bits; only the four LSBs can change.
H.4.3
EPROM/EEPROM control register
bit 5
EPROM/EEPROM/ECLK control
E6LAT E6PGM ECLK E1ERA E1LAT E1PGM u000 0000
14
Freescale H-8
lim re P
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bit 1
bit 0
State on reset
MC68HC705B32
MC68HC05B6 Rev. 4.1
E6LAT -- EPROM programming latch enable bit 1 (set) - Address and up to sixteen data bytes can be latched into the EPROM for further programming providing the E6PGM bit is cleared. When programming the EPROM, all other 15 addresses must be latched with the erased state ($00) or corruption may occur. Data can be read from the EPROM or firmware ROM; the E6PGM bit is reset to zero when E6LAT is `0'.
0 (clear) -
STOP, power-on and external reset clear the E6LAT bit. Note:
After the tERA1 erase time or tPROG1 programming time, the E6LAT bit has to be reset to zero in order to clear the E6PGM bit.
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0 1 1
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E6PGM -- EPROM program enable bit This bit is the EPROM program enable bit. It can be set to `1' to enable programming only after E6LAT is set and at least one byte is written to the EPROM. It is not possible to clear this bit using software but clearing E6LAT will always clear E6PGM.
Table H-2 EPROM control bits description
E6LAT E6PGM
Note:
All combinations are not shown in the above table, since the E6PGM bit is cleared when the E6LAT bit is at zero, and will result in a read condition.
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0 1
0
lim e
Description
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Read/execute in EPROM Ready to write address/data to EPROM
programming in progress
ECLK See Section 4.3. E1ERA -- EEPROM erase/programming bit
Providing the E1LAT and E1PGM bits are at logic one, this bit indicates whether the access to the EEPROM is for erasing or programming purposes. 1 (set) - An erase operation will take place. A programming operation will take place.
0 (clear) -
Once the program/erase EEPROM address has been selected, E1ERA cannot be changed.
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14
MC68HC05B6 Rev. 4.1
MC68HC705B32
Freescale H-9
E1LAT -- EEPROM programming latch enable bit 1 (set) - Address and data can be latched into the EEPROM for further program or erase operations, providing the E1PGM bit is cleared. Data can be read from the EEPROM. The E1ERA bit and the E1PGM bit are reset to zero when E1LAT is `0'.
0 (clear) -
STOP, power-on and external reset clear the E1LAT bit. Note:
After the tERA1 erase time or tPROG1 programming time, the E1LAT bit has to be reset to zero in order to clear the E1ERA bit and the E1PGM bit.
E1PGM -- EEPROM charge pump enable/disable 1 (set) -
Internal charge pump generator switched on. Internal charge pump generator switched off.
lim re P lim re P
E1LAT E1PGM 0 1 1 0 0 1 Read condition 1 1 0 1
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0 (clear) -
When the charge pump generator is on, the resulting high voltage is applied to the EEPROM array. This bit cannot be set before the data is selected, and once this bit has been set it can only be cleared by clearing the E1LAT bit. A summary of the effects of setting/clearing bits 0, 1 and 2 of the control register are given in Table H-3.
Table H-3 EEPROM control bits description
Description
E1ERA 0 0 0 1 1
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Ready to load address/data for program/erase Byte programming in progress Ready for byte erase (load address) Byte erase in progress
Note:
The E1PGM and E1ERA bits are cleared when the E1LAT bit is at zero.
14
Freescale H-10
lim re P
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MC68HC705B32
MC68HC05B6 Rev. 4.1
H.4.4
Mask option register
Address bit 7 bit 6 bit 5
Mask option register (MOR)(1)
$7FDE
(1) Because this register is implemented in EPROM, reset has no effect on the individual bits.
RTIM
This bit can modify the time tPORL, where the RESET pin is kept low after a power-on reset. 1 (set) - tPORL = 16 cycles.
0 (clear) - RWAT
tPORL = 4064 cycles.
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bit 4 bit 3 bit 2
bit 1
bit 0
State on reset
RTIM RWAT WWAT PBPD PCPD Not affected
This bit can modify the status of the watchdog counter after reset. Usually, the watchdog system is disabled after power-on or external reset but when this bit is set, it will be active immediately after the following resets (except in bootstrap mode). WWAT
This bit can modify the status of the watchdog counter in WAIT mode. Normally, the watchdog system is disabled in WAIT mode but when this bit is set, the watchdog will be active in WAIT mode. PBPD
This bit, when programmed, connects a resistive pull-down on all 8 pins of port B. This pull-down, RPD, is active on a given pin only while it is an input. PCPD This bit, when programmed, connects a resistive pull-down on all 8 pins of port C. This pull-down, RPD, is active on a given pin only while it is an input.
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MC68HC05B6 Rev. 4.1
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14
Freescale H-11
MC68HC705B32
H.4.5
Options register (OPTR)
Address Options (OPTR)(1) $0100 bit 7 bit 6 bit 5
(1) Because this register is implemented in EEPROM, reset has no effect on the individual bits.
EE1P - EEPROM protect bit
In order to achieve a higher degree of protection, the EEPROM is effectively split into two parts, both working from the VPP1 charge pump. Part 1 of the EEPROM array (32 bytes from $0100 to $011F) cannot be protected; part 2 (224 bytes from $0120 to $01FF) is protected by the EE1P bit of the options register. 1 (set) - Part 2 of the EEPROM array is not protected; all 256 bytes of EEPROM can be accessed for any read, erase or programming operations. Part 2 of the EEPROM array is protected; any attempt to erase or program a location will be unsuccessful.
lim re P lim re P
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bit 4 bit 3 bit 2
bit 1
bit 0
State on reset
EE1P
SEC Not affected
0 (clear) -
When this bit is set to 1 (erased), the protection will remain until the next power-on or external reset. EE1P can only be written to `0' when the E1LAT bit in the EEPROM control register is set. Note: The EEPROM1 protect function is disabled while in bootstrap mode.
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SEC -- Secure bit
This bit allows the EPROM and EEPROM1 to be secured from external access. When this bit is in the erased state (set), the EPROM and EEPROM1 content is not secured and the device may be used in non user mode. When the SEC bit is programmed to `zero', the EPROM and EEPROM1 content is secured by prohibiting entry to the non user mode. To deactivate the secure bit, the EPROM has to be erased by exposure to a high density ultraviolet light, and the device has to be entered into the EPROM erase verification mode with PD1 set. When the SEC bit is changed, its new value will have no effect until the next power-on or external reset. 1 (set) - EEPROM/EPROM not protected. EEPROM/EPROM protected.
0 (clear) -
14
Freescale H-12
lim re P
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MC68HC705B32
MC68HC05B6 Rev. 4.1
H.5
Bootstrap mode
Oscillator divide-by-two is forced in bootstrap mode.
The 432 bytes of self-check firmware on the MC68HC05B6 are replaced by 654 bytes of bootstrap firmware. A detailed description of the modes of operation within bootstrap mode is given below. The bootstrap program in mask ROM address locations $0200 to $024F, $03B0 to $3FFF, $7E00 to $7FDD and $7FE0 to $7FEF can be used to program the EPROM and the EEPROM, to check if the EPROM is erased or to load and execute data in RAM. After reset, while going to the bootstrap mode, the vector located at address $7FEE and $7FEF (RESET) is fetched to start execution of the bootstrap program. To place the part in bootstrap mode, the IRQ pin should be at 2xVDD with the TCAP1 pin `high' during transition of the RESET pin from low to high. The hold time on the IRQ and TCAP1 pins is two clock cycles after the external RESET pin is brought high.
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x 0 1 0 1 x 0 x
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When the MC68HC705B32 is placed in the bootstrap mode, the bootstrap reset vector will be fetched and the bootstrap firmware will start to execute. Table H-4 shows the conditions required to enter each level of bootstrap mode on the rising edge of RESET.
Table H-4 Mode of operation selection
IRQ pin VSS to VDD 2xVDD 2xVDD 2xVDD 2xVDD 2xVDD 2xVDD 2xVDD x = Don't care TCAP1 pin PD1 PD2 PD3 PD4 VSS to VDD VDD VDD VDD VDD VDD VDD VDD x x x 0 0 1 1 1 1 x 0 0 0 0 1 0 1 x
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Single chip 0 0 0 0 1 1
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Mode
Erased EPROM verification EPROM verification; erase EEPROM; EPROM/EEPROM parallel program/verify Erased EPROM verification; no EEPROM erase if SEC is zero (parallel mode) Erased EPROM verification; erase EEPROM; EPROM parallel program/verify (no E2)
Jump to start of RAM ($0051); SEC bit = ACTIVE EPROM and EEPROM verification; SEC bit = ACTIVE (parallel mode) Serial RAM load/execute - similar to MC68HC05B6 but can fill RAM I, II and III
The bootstrap program will first copy part of itself in RAM (except `RAM parallel load'), as the program cannot be executed in ROM during verification/programming of the EPROM. It will then set the TCMP1 output to a logic high level, unlike the MC68HC05B6 which keeps TCMP1 low. This can be used to distinguish between the two circuits and, in particular, for selection of the VPP level and current capability.
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14
Freescale H-13
MC68HC05B6 Rev. 4.1
MC68HC705B32
Reset
IRQ at 2xVDD? Y
N Y
TCAP1=VDD? Y
lim re P
N SEC bit active?
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User mode N Non-user mode
Bootstrap mode
Y
Parallel E/EEPROM bootstrap Erased EPROM verification
Y Red LED on
PD3 set? N N PD2 set? Y PD1 set? Y
SEC bit active? N
PD4 set? N N
Red LED on
N
EPROM erased? Y
Green LED on
lim re P
N PD1 set? N N B N
PD2 set?
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Y Y Y Red LED on Y A
Serial RAM load/execute
Non-user mode
Jump to RAM ($0051)
SEC bit active?
PD4 set? Erase EEPROM1
Red LED off
14
Freescale H-14
lim re P
C
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MC68HC05B6 Rev. 4.1
Figure H-3 Modes of operation flow chart (1 of 2)
MC68HC705B32
C
Y
PD2 set?
Base address = $400 (EPROM only)
P
A B
lim re
PD2 set? N
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N Base address = $400 (EPROM only)
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lim re
Data verified? Y Green LED on
Base address = $100 (EPROM and EEPROM)
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N N Red LED on
Y
Base address = $400 (EPROM only)
Figure H-4 Modes of operation flow chart (2 of 2)
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MC68HC05B6 Rev. 4.1
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14
Freescale H-15
MC68HC705B32
H.5.1
Erased EPROM verification
If a non $00 byte is detected, the red LED will be turned on and the routine will stop (see Figure H-3 and Figure H-4). Only when the whole EPROM content is verified as erased will the green LED be turned on. PD1 is then checked. If PD1=0, the bootstrap program stops here and no programming occurs until such time as a high level is sensed on PD1. If PD1 = 1, the bootstrap program proceeds to erase the EEPROM1 for a nominal 2.5 seconds (4.0 MHz crystal). It is then checked for complete erasure; if any EEPROM byte is not erased, the program will stop before erasing the SEC byte. When both EPROM and EEPROM1 are completely erased and the security bit is cleared the programming operation can be performed. A schematic diagram of the circuit required for erased EPROM verification is shown in Figure H-7.
H.5.2
EPROM/EEPROM parallel bootstrap
lim re P lim re P
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Within this mode there are various subsections which can be utilised by correctly configuring the port pins shown in Table H-4. The erased EPROM verification program will be executed first as described in Section H.5.1. When PD2=0, the programming time is set to 5 milliseconds with the bootstrap program and verify for the EPROM taking approximately 15 seconds. The EPROM will be loaded in increasing address order with non EPROM segments being skipped by the loader. Simultaneous programming is performed by reading sixteen bytes of data before actual programming is performed, thus dividing the loading time of the internal EPROM by 16. If any block of 16 EPROM bytes or 1 EEPROM byte of data is in the erased state, no programming takes place, thus speeding up the execution time. Parallel data is entered through Port A, while the 15-bit address is output on port B, PC0 to PC4 and TCMP1 and TCMP2. If the data comes from an external EPROM, the handshake can be disabled by connecting together PC5 and PC6. If the data is supplied by a parallel interface, handshake will be provided by PC5 and PC6 according to the timing diagram of Figure H-5 (see also Figure H-6). During programming, the green LED will flash at about 3 Hz.
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Upon completion of the programming operation, the EPROM and EEPROM1 content will be checked against the external data source. If programming is verified the green LED will stay on, while an error will cause the red LED to be turned on. Figure H-7 is a schematic diagram of a circuit which can be used to program the EPROM or to load and execute data in the RAM. Note: The entire EPROM and EEPROM1 can be loaded from the external source; if it is desired to leave a segment undisturbed, the data for this segment should be all $00s for EPROM data and all $FFs for EEPROM1 data.
14
Freescale H-16
lim re P
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MC68HC705B32
MC68HC05B6 Rev. 4.1
Address
HDSK out (PC5) Data
HDSK in (PC6) F29
P
tCOOE tADE tDHE
lim re
Data read tCOOE
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Data read
Figure H-5 Timing diagram with handshake
Address
Data
tADE max (address to data delay) tDHA min (data hold time) tCOOE (load cycle time) tCDDE (programming cycle time)
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lim re
tDHE
tADE
tADE
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tCOOE tDHE tADE
tCDDE
tDHE
5 machine cycles 117 machine cycles < tCOOE < 150 machine cycles tCOOE + tPROG (5ms nominal for EPROM; 10ms for EEPROM1))
14 machine cycles
1 machine cycle = 1/(2f0(Xtal))
Figure H-6 Parallel EPROM loader timing diagram
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MC68HC05B6 Rev. 4.1
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14
Freescale H-17
MC68HC705B32
100k
lim re P
RESET RUN 1N914 1k 1N914 1.0F + red LED 0.01F 470 470 green LED
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100F +
P1
1 2 3
GND +5V VPP
TCAP1 VRH VDD IRQ RESET NC TCMP1 VPP1 PLMA PLMB OSC1 OSC2 RDI VRL TCAP2 PD7 PD6 PD5 PD3 PD2 PD1 PD0
4.0 MHz 22pF 22pF Verify EPROM Erase check & boot 47F +
Boot red LED -- programming failed green LED -- programming OK Erase check green LED -- EPROM erased red LED -- EPROM not erased
+5V 1 27 28 VPP PGM VCC A14 26 A13 A0 A1 A2 A3 A4 20 CE A5 A6 27C256 A7
MC68HC705B32 MCU
lim re P
10 9 8 7 6 5 4 3 D0 D1 D2 D3 D4 D5 D6 D7 11 12 13 15 16 17 18 19 OE 22
SCLK TDO TCMP2 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
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RAM
EPROM erase check
Program EPROM
EPROM
1N5819
PD4
1 k BC309C
10k
VPP6
12 k 4k7
PC7
4k7
BC239C
1nF
+
+5V
100 k HDSK out Short circuit if handshake not used
25 24 21 23 2
PC5 PC6 PC4 PC3 PC2 PC1 PC0 A12 A11 A10 A9 A8
A8 A9 A10 A11 A12 GND 14
Note:
This circuit is recommended for programming only at 25C and not for use in the end application, or at temperatures other than 25C. If used in the end application, VPP6 should be tied to VDD to avoid damaging the device.
14
Freescale H-18
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VSS
HDSK in
Figure H-7 EPROM parallel bootstrap schematic diagram
MC68HC705B32
MC68HC05B6 Rev. 4.1
H.5.3
Serial RAM loader
This mode is similar to the RAM load/execute program for the MC68HC05B6 described in Section 2.2, with the additional features listed below. Table H-4 shows the entry conditions required for this mode. If the first byte is less than $B0, the bootloader behaves exactly as the MC68HC05B6, i.e. count byte followed by data stored in $0050 to $00FF. If the count byte is larger than RAM I (176 bytes) then the code continues to fill RAM II then RAM III. In this case the count byte is ignored and the program execution begins at $0051 once the total RAM area is filled or if no data is received for 5 milliseconds. The user must take care when using branches or jumps as his code will be relocated in RAM I, II and III. If the user intends to use the stack in his program, he should send NOP's to fill the desired stack area. In the RAM bootloader mode, all interrupt vectors are mapped to pseudo-vectors in RAM (see Table H-5). This allows programmers to use their own service-routine addresses. Each pseudo-vector is allowed three bytes of space rather than the two bytes for normal vectors, because an explicit jump (JMP) opcode is needed to cause the desired jump to the users service-routine address.
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Table H-5 Bootstrap vector targets in RAM
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H.5.3.1
lim re
SCI interrupt Timer overflow Timer output compare Timer input capture IRQ SWI
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$0063 $0060 $005D $005A $0057 $0054
Vector targets in RAM
Jump to start of RAM ($0051)
The Jump to start of RAM program will be executed when bring the device out of reset with PD2 and PD3 at `1' and PD4 at `0'.
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MC68HC05B6 Rev. 4.1
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14
Freescale H-19
MC68HC705B32
RESET 100k 1k
RUN 1N914 1.0F +
22 19
1N914
TCAP1 VRH VDD IRQ
0.01F
Erase check Green LED -- EPROM erased Red LED -- EPROM not erased
lim re P
Red LED 470 470
18 RESET
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10nF +
P1
1 2 3
GND +5V VPP
8
10
47F
OSC1
47F
+
20 21
PLMA PLMB
OSC2
4.0 MHz 22pF 22pF
Green LED
PD3
MC68HC705B32 MCU (socket)
Serial boot Flashing green LED -- programming Green LED -- programming ended
Erase check and serial boot EPROM erase check
9600 BD 8-bit no parity
8 5 7 3 2 1 2 x 3K
lim re P
31 30 29 28 27 26 25 24 14 13 12 5 4 3 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 +5V
16 1 3 4 5 12 11 + 22F + 22F
39 38 37 36 35 34 33 32
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7
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PD4
Erase check & serial boot
Serial boot
1 k BC309C 1N5819 12 k
10k
VPP6
4k7
PC7
BC239C
1nF
+
4k7
22F + 2
RS232 Connector
22F + 6 13 14
MAX 232
PD0 PD1 PD2 PD5 PD6 PD7
PC6 PC5 PC4 PC3 PC2 PC1 PC0
43 44 45 46 47 48 49
50 RDI 52 TDO VSS 41
15
Note:
14
Freescale H-20
A minimum VDD voltage must be applied to the VPP6 pin at all times, including power-on, as a lower voltage could damage the device. Unless otherwise stated, EPROM programming is guaranteed at ambient (25C) temperature only
lim re P
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VPP1 23 TCAP2 2 TCMP1 1 TCMP2 51 SCLK 40 NC VRL
7
Figure H-8 RAM load and execute schematic diagram
MC68HC705B32
MC68HC05B6 Rev. 4.1
tCR
Address PC5 out tHO
Data PC6 in
r P
lim e
tADR tDHR tHI max tEXR max
ry a in ry a in ry a in
14
Freescale H-21
PD4
tADR max (address to data delay; PC6=PC5) tDHR min (data hold time) tCR (load cycle time; PC6=PC5) tHO (PC5 handshake out delay)
16 machine cycles 4 machine cycles 49 machine cycles
tHI max (PC6 handshake in, data hold time)
tEXR max (max delay for transition to be recognised during this cycle; PC6=PC5
P
lim re
5 machine cycles
10 machine cycles
30 machine cycles
1 machine cycle = 1/(2f0(Xtal))
Figure H-9 Parallel RAM loader timing diagram
P
MC68HC05B6 Rev. 4.1
lim re
MC68HC705B32
H.6
Absolute maximum ratings
Table H-6 Absolute Maximum ratings
Rating Supply voltage(1) Input voltage (Except VPP1 and VPP6) Input voltage - Self-check mode (IRQ pin only) Operating temperature range - Standard (MC68HC705B32) - Extended (MC68HC705B32C) Storage temperature range Symbol VDD VIN VIN TA
Current drain per pin (excluding VDD and VSS)(2) - Source - Sink (1) All voltages are with respect to VSS.
lim re P lim re P
ry a in
Value - 0.5 to +7.0 VSS - 0.5 to VDD + 0.5 VSS - 0.5 to 2VDD + 0.5 TL to TH 0 to +70 -40 to +85 - 65 to +150 25 45
Unit V V V C C mA mA
TSTG ID IS
(2) Maximum current drain per pin is for one pin at a time, limited by an external resistor.
Note:
This device contains circuitry designed to protect against damage due to high electrostatic voltages or electric fields. However, it is recommended that normal precautions be taken to avoid the application of any voltages higher than those given in the maximum ratings table to this high impedance circuit. For maximum reliability all unused inputs should be tied to either VSS or VDD.
ry a in
14
Freescale H-22
lim re P
ry a in
MC68HC05B6 Rev. 4.1
MC68HC705B32
H.7
DC electrical characteristics
Table H-7 DC electrical characteristics for 5V operation
(VDD = 5 Vdc 10%, VSS = 0 Vdc, -40 to +85C) Characteristic(1) Output voltage ILOAD = - 10 A ILOAD = +10 A Output high voltage (ILOAD = 0.8mA) PA0-7, PB0-7, PC0-7, TCMP1, TCMP2 Output high voltage (ILOAD = 1.6mA) TDO, SCLK, PLMA, PLMB Output high voltage (ILOAD = -300A) OSC2 Output low voltage (ILOAD = 1.6mA) PA0-7, PB0-7, PC0-7, TCMP1, TCMP2, TDO, SCLK, PLMA, PLMB Output low voltage (ILOAD = 1.6mA) RESET Output low voltage (ILOAD = -100A) OSC2 Input high voltage PA0-7, PB0-7, PC0-7, PD0-7, OSC1, IRQ, RESET, TCAP1, TCAP2, RDI Input low voltage PA0-7, PB0-7, PC0-7, PD0-7,OSC1, IRQ, RESET, TCAP1, TCAP2, RDI Supply current(3) (For Guidance Only) RUN (SM = 0) (See Figure 11-1) RUN (SM = 1) (See Figure 11-2) WAIT (SM = 0) (See Figure 11-3) WAIT (SM = 1) (See Figure 11-4) STOP 0 to 70 (standard) - 40 to 85 (extended) High-Z leakage current PA0-7, PB0-7, PC0-7, TDO, RESET, SCLK Input current Port B and port C pull-down (VIN =VIH) Input current (0 to 70) IRQ, OSC1, TCAP1, TCAP2, RDI, PD0/AN0-PD7/AN7 (channel not selected) Input current (- 40 to 85) IRQ, OSC1, TCAP1, TCAP2, RDI, PD0/AN0-PD7/AN7 (channel not selected) Capacitance Ports (as input or output), RESET, TDO, SCLK IRQ, TCAP1, TCAP2, OSC1, RDI PD0/AN0-PD7/AN7 (A/D off) PD0/AN0-PD7/AN7 (A/D on) Symbol VOH VOL Min Typ(2) -- -- Max -- 0.1 -- -- -- 0.4 1 -- V V mA mA mA mA A A A A 1 5 A A V Unit V
r P
lim e
VOH VOH VOH VOL VOL VOL VIH VIL IDD IDD IDD IDD IDD IDD IIL IRPD IIN IIN
ry a in
VDD - 0.1 -- VDD - 0.8 VDD - 0.8 VDD - 0.8 -- -- -- VDD - 0.4 VDD - 0.4 VDD - 0.3 0.1 0.4 TBD -- -- 0.7VDD VSS -- -- -- -- -- -- --
V
r P
lim e
COUT COUT CIN CIN
ry a in
6 1.5 2 1 10 10 0.2 80
VDD
0.2VDD TBD TBD TBD TBD TBD TBD 1
(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switching currents inherent in CMOS designs (see Section 2). (2) Typical values are at mid point of voltage range and at 25C only.
P
lim re
ry a in
-- -- 0.2 -- -- -- -- -- -- -- 12 22
12 8 -- --
pF pF pF pF
14
MC68HC05B6 Rev. 4.1
MC68HC705B32
Freescale H-23
(3) RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 2.0 MHz); all inputs 0.2 V from rail; no DC loads; maximum load on outputs 50pF (20pF on OSC2). STOP /WAIT IDD: all ports configured as inputs; VIL = 0.2 V and VIH = VDD - 0.2 V: STOP IDD measured with OSC1 = VDD. WAIT IDD is affected linearly by the OSC2 capacitance.
lim re P lim re P lim re P
Freescale H-24
ry a in
ry a in ry a in
MC68HC05B6 Rev. 4.1
14
MC68HC705B32
Table H-8 DC electrical characteristics for 3.3V operation
(VDD = 3.3Vdc 10%, VSS = 0Vdc, TA = -40 to +85C) Symbol Characteristic(1) Output voltage ILOAD = - 10 A VOH ILOAD = +10 A VOL Output high voltage (ILOAD = 0.8mA) PA0-7, PB0-7, PC0-7, TCMP1, TCMP2 VOH Output high voltage (ILOAD = 1.6mA) TDO, SCLK, PLMA, PLMB VOH Output low voltage (ILOAD = 1.6mA) PA0-7, PB0-7, PC0-7, TCMP1, TCMP2, VOL TDO, SCLK, PLMA, PLMB Output low voltage (ILOAD = 1.6mA) VOL RESET Input high voltage PA0-7, PB0-7, PC0-7, PD0-7, OSC1, VIH IRQ, RESET, TCAP1, TCAP2, RDI Input low voltage PA0-7, PB0-7, PC0-7, PD0-7, OSC1, IRQ, VIL RESET, TCAP1, TCAP2, RDI Supply current(3) (For Guidance Only) RUN (SM = 0) (See Figure 11-1) IDD RUN (SM = 1) (See Figure 11-2) IDD WAIT (SM = 0) (See Figure 11-3) IDD WAIT (SM = 1) (See Figure 11-4) IDD STOP 0 to 70 (standard) IDD - 40 to 85 (extended) IDD High-Z leakage current PA0-7, PB0-7, PC0-7, TDO, RESET, SCLK IIL Input current (0 to 70) IRQ, OSC1, TCAP1, TCAP2, RDI, IIN PD0/AN0-PD7/AN7 (channel not selected) Input current (- 40 to 125) IRQ, OSC1, TCAP1, TCAP2, RDI, IIN PD0/AN0-PD7/AN7 (channel not selected) Capacitance Ports (as input or output), RESET, TDO, COUT SCLK COUT IRQ, TCAP1, TCAP2, OSC1, RDI CIN PD0/AN0-PD7/AN7 (A/D off) CIN PD0/AN0-PD7/AN7 (A/D on)
r P
lim e lim e
ry a in
Min Typ(2) -- -- VDD - 0.1 -- VDD - 0.3 VDD - 0.3 -- VDD - 0.1 VDD - 0.1 0.1 0.2 0.7VDD VSS -- -- -- -- -- -- -- -- -- --
Max -- 0.1 -- -- 0.3 0.6 VDD
Unit V
V
V
V
ry a in
3 1 1.5 0.5 10 10 0.2 0.2 -- --
0.2VDD TBD TBD TBD TBD TBD TBD 1 1 5
V
mA mA mA mA A A A A A
r P
(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switching currents inherent in CMOS designs (see Section 2). (2) Typical values are at mid point of voltage range and at 25C only. (3) RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 2.0 MHz); all inputs 0.2 V from rail; no DC loads; maximum load on outputs 50pF (20pF on OSC2). STOP /WAIT IDD: all ports configured as inputs; VIL = 0.2 V and VIH = VDD - 0.2 V: STOP IDD measured with OSC1 = VDD. WAIT IDD is affected linearly by the OSC2 capacitance.
P
lim re
ry a in
-- -- -- -- -- -- 12 22
12 8 -- --
pF pF pF pF
14
MC68HC05B6 Rev. 4.1
MC68HC705B32
Freescale H-25
H.8
A/D converter characteristics
Table H-9 A/D characteristics for 5V operation
(VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = -40 to +85C) Characteristic Resolution Non-linearity Number of bits resolved by the A/D
Max deviation from the best straight line through the A/D transfer characteristics (VRH = VDD and VRL = 0V) Uncertainty due to converter resolution
Quantization error Absolute accuracy
Difference between the actual input voltage and the full-scale equivalent of the binary code output code for all errors Analog input voltage range Maximum analog reference voltage Minimum analog reference voltage Minimum difference between VRH and VRL
lim re P lim re P
Parameter
ry a in
Min 8 -- -- -- VRL VRL
Max -- 0.5 0.5 1 VRH VDD + 0.1 VRH -- 32 32
Unit Bit LSB LSB LSB V V V V tCYC s
Conversion range VRH VRL VR Conversion time
Total time to perform a single analog to digital conversion a. External clock (OSC1, OSC2) b. Internal RC oscillator Conversion result never decreases with an increase in input voltage and has no missing codes Conversion result when VIN = VRL Conversion result when VIN = VRH
Monotonicity Zero input reading Full scale reading
ry a in
VSS - 0.1 3 -- -- 00 -- -- -- -- --
GUARANTEED -- FF 12 12 12 1 Hex Hex tCYC s pF A
Sample acquisition time Analog input acquisition sampling a. External clock (OSC1, OSC2) b. Internal RC oscillator(1) Input leakage(2)
Sample/hold capacitance Input capacitance on PD0/AN0-PD7/AN7
Input leakage on A/D pins PD0/AN0-PD7/AN7, VRL, VRH
(1) Source impedances greater than 10k will adversely affect internal charging time during input sampling. (2) The external system error caused by input leakage current is approximately equal to the product of R source and input current. Input current to A/D channel will be dependent on external source impedance (see Figure 8-2).
14
Freescale H-26
lim re P
ry a in
MC68HC705B32
MC68HC05B6 Rev. 4.1
Table H-10 A/D characteristics for 3.3V operation
(VDD = 3.3 Vdc 10%, VSS = 0 Vdc, TA = -40 to +85C) Characteristic Resolution Non-linearity Parameter Number of bits resolved by the A/D
Max deviation from the best straight line through the A/D transfer characteristics (VRH = VDD and VRL = 0V) Uncertainty due to converter resolution
Quantization error Absolute accuracy
Difference between the actual input voltage and the full-scale equivalent of the binary code output code for all errors Analog input voltage range Maximum analog reference voltage Minimum analog reference voltage Minimum difference between VRH and VRL Total time to perform a single analog to digital conversion Internal RC oscillator Conversion result never decreases with an increase in input voltage and has no missing codes Conversion result when VIN = VRL Conversion result when VIN = VRH
Conversion range VRH VRL VR Conversion time Monotonicity Zero input reading Full scale reading
r P
lim e
ry a in
Min 8 -- -- -- VRL VRL VSS - 0.1 3 --
Max -- 1 1 2 VRH VDD + 0.1 VRH -- 32
Unit Bit LSB LSB LSB V V V V s
Sample acquisition time Analog input acquisition sampling Internal RC oscillator(1) Input leakage(2)
Sample/hold capacitance Input capacitance on PD0/AN0-PD7/AN7
Input leakage on A/D pins PD0/AN0-PD7/AN7, VRL, VRH
(1) Source impedances greater than 10k will adversely affect internal charging time during input sampling. (2) The external system error caused by input leakage current is approximately equal to the product of R source and input current. Input current to A/D channel will be dependent on external source impedance (see Figure 8-2).
r P
lim e
ry a in
00 -- -- -- --
GUARANTEED -- FF 12 12 1 Hex Hex s pF A
P
MC68HC05B6 Rev. 4.1
lim re
ry a in
14
Freescale H-27
MC68HC705B32
H.9
Control timing
Table H-11 Control timing for 5V operation
(VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = -40 to +85C) Characteristic Frequency of operation Crystal option External clock option
Symbol fOSC fOSC fOP fOP
Internal operating frequency (fOSC/2) Using crystal Using external clock Cycle time (see Figure 9-1)
Crystal oscillator start-up time (see Figure 9-1) Stop recovery start-up time (crystal oscillator) RC oscillator stabilization time A/D converter stabilization time External RESET input pulse width Power-on RESET output pulse width 4064 cycle 16 cycle Watchdog RESET output pulse width Watchdog time-out EEPROM byte erase time 0 to 70 (standard) - 40 to 85 (extended)
lim re P lim re P
ry a in
Min -- dc -- dc 476 -- Max 4.2 4.2 2.1 2.1 -- 100 100 5 500 3.0 --
Unit MHz MHz MHz MHz ns ms ms s s tCYC tCYC tCYC tCYC tCYC ms ms ms ms tCYC ns tCYC ns tCYC ns cycles years
tCYC
tOXOV tILCH tADRC tRL
tADON
tPORL tPORL tDOG tERA tERA
tDOGL
ry a in
4064 16 1.5 6144 10 10 10 10 4 125 --(3) 125 --(4) 90 -- -- -- 7168 -- -- -- -- -- -- -- -- -- --
EEPROM byte program time(1) 0 to 70 (standard) - 40 to 85 (extended) Timer (see Figure H-10) Resolution(2) Input capture pulse width Input capture pulse period Interrupt pulse period OSC1 pulse width(5) Write/Erase endurance(6)(7) Data retention(6)(7)
tPROG tPROG
tRESL tTH, tTL tTLTL tILIH tILIL -- --
Interrupt pulse width (edge-triggered)
tOH, tOL
14
Freescale H-28
(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when programming the EEPROM. (2) Since a 2-bit prescaler in the timer must count four external cycles (tCYC), this is the limiting factor in determining the timer resolution. (3) The minimum period tTLTL should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 tCYC. (4) The minimum period tILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 tCYC. (5) tOH and tOL should not total less than 238ns. (6) At a temperature of 85C (7) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information.
lim re P
ry a in
10000 10
MC68HC705B32
MC68HC05B6 Rev. 4.1
Table H-12 Control timing for operation at 3.3V
(VDD = 3.3Vdc 10%, VSS = 0 Vdc, TA = -40 to +85C) Characteristic Frequency of operation Crystal option External clock option
Symbol fOSC fOSC fOP fOP
Internal operating frequency (fOSC/2) Using crystal Using external clock Cycle time (see Figure 9-1)
Crystal oscillator start-up time (see Figure 9-1) Stop recovery start-up time (crystal oscillator) RC oscillator stabilization time A/D converter stabilization time External RESET input pulse width Power-on RESET output pulse width 4064 cycle 16 cycle Watchdog RESET output pulse width Watchdog time-out EEPROM byte erase time 0 to 70 (standard) - 40 to 85 (extended)
r P
lim e
ry a in
Min -- dc -- dc -- Max 2.0 2.0 1.0 1.0 -- 100 100 5 500 3.0 4064 16 1.5 6144 30 30 30 30 4 250 --(3) 250 --(4) 100 10000 10 -- -- -- 1000
Unit MHz MHz MHz MHz ns ms ms s s tCYC tCYC tCYC tCYC tCYC ms ms ms ms tCYC ns tCYC ns tCYC ns cycles years
tCYC
tOXOV tILCH tADRC
tADON tRL tPORL tPORL tDOG
tDOGL
EEPROM byte program time(1) 0 to 70 (standard) - 40 to 85 (extended) Timer (see Figure H-10) Resolution(2) Input capture pulse width Input capture pulse period Interrupt pulse period OSC1 pulse width(5) Write/Erase endurance(6)(7) Data retention(6)(7)
Interrupt pulse width (edge-triggered)
P
lim re
tERA tERA
ry a in
-- 7168 -- -- -- -- -- -- -- -- -- --
tPROG tPROG
tRESL tTH, tTL tTLTL tILIH tILIL
tOH, tOL -- --
(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when programming the EEPROM. (2) Since a 2-bit prescaler in the timer must count four external cycles (tCYC), this is the limiting factor in determining the timer resolution. (3) The minimum period tTLTL should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 tCYC. (4) The minimum period tILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 tCYC. (5) tOH and tOL should not total less than 500ns. (6) At a temperature of 85C
(7) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information.
P
lim re
ry a in
14
Freescale H-29
MC68HC05B6 Rev. 4.1
MC68HC705B32
tTLTL External signal (TCAP1, TCAP2)
tTH
H.10
EPROM electrical characteristics
Table H-13 DC electrical characteristics for 5V operation
(VDD = 5 Vdc 10%, VSS = 0 Vdc, TA = 25C) Characteristic(1) EPROM Absolute maximum voltage Programming voltage Programming current Read voltage Symbol VPP6 max VPP6 IPP6 VPP6R Min VDD 15 -- VDD Typ(2) -- 15.5 50 VDD Max 18 16 64 VDD Unit V V mA V
lim re P lim re P
Characteristic Characteristic
Figure H-10 Timer relationship
ry a in ry a in
Min 5 Max 20 Min 5 Max 20
tTL
(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switching currents inherent in CMOSBLANKSection 2). THIS PAGE LEFT designs (see INTENTIONALLY (2) Typical values are at mid point of voltage range and at 25C only.
Table H-14 Control timing for 5V operation
Symbol tPROG Unit ms
(VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = 25C) EPROM programming time
Table H-15 Control timing for 3.3V operation
(VDD = 3.3 Vdc 10%, VSS = 0 Vdc, TA = 25C) EPROM programming time Symbol tPROG
14
Freescale H-30
lim re P
ry a in
Unit ms
MC68HC705B32
MC68HC05B6 Rev. 4.1
I
HIGH SPEED OPERATION
This section contains the electrical specifications and associated timing information for high speed versions of the MC68HC05B6, MC68HC05B8 and MC68HC05B16 (fOSC max = 8 MHz). The ordering information for these devices is contained in Table I-1.
Table I-1 Ordering information
Suffix 0 to 70C FN FU B FN FU B FN FU B Suffix -40 to +85C CFN CFU CB CFN CFU CB CFN CFU CB
Device title MC68HC05B6
Package 52-pin PLCC 64-pin QFP 56-pin SDIP 52-pin PLCC
MC68HC05B8
64-pin QFP 56-pin SDIP 52-pin PLCC
MC68HC05B16
64-pin QFP 56-pin SDIP
Note:
The high speed version has the same device title as the standard version. High speed operation is selected via a check-box on the order form and will be confirmed on the listing verification form.
MC68HC05B6 Rev. 4.1
HIGH SPEED OPERATION
Freescale I-1
15
I.1
DC electrical characteristics
Table I-2 DC electrical characteristics for 5V operation
(VDD = 5 Vdc 10%, VSS = 0 Vdc, TA = -40 to +85C) Characteristic(1) Output voltage ILOAD = - 10 A ILOAD = +10 A Output high voltage (ILOAD = 0.8mA) PA0-7, PB0-7, PC0-7, TCMP1, TCMP2 Output high voltage (ILOAD = 1.6mA) TDO, SCLK, PLMA, PLMB Output low voltage (ILOAD = 1.6mA) PA0-7, PB0-7, PC0-7, TCMP1, TCMP2, TDO, SCLK, PLMA, PLMB Output low voltage (ILOAD = 1.6mA) RESET Input high voltage PA0-7, PB0-7, PC0-7, PD0-7, OSC1, IRQ, RESET, TCAP1, TCAP2, RDI Input low voltage PA0-7, PB0-7, PC0-7, PD0-7, OSC1, IRQ, RESET, TCAP1, TCAP2, RDI Supply current(3) RUN (SM = 0) (See Figure 11-1) RUN (SM = 1) (See Figure 11-2) WAIT (SM = 0) (See Figure 11-3) WAIT (SM = 1) (See Figure 11-4) STOP 0 to 70 (standard) - 40 to 85 (extended) High-Z leakage current PA0-7, PB0-7, PC0-7, TDO, RESET, SCLK Input current (0 to 70) IRQ, OSC1, TCAP1, TCAP2, RDI, PD0/AN0-PD7/AN7 (channel not selected) Capacitance Ports (as input or output), RESET, TDO, SCLK IRQ, TCAP1, TCAP2, OSC1, RDI PD0/AN0-PD7/AN7 (A/D off) PD0/AN0-PD7/AN7 (A/D on) Symbol VOH VOL VOH VOH VOL VOL VIH Min VDD - 0.1 -- VDD - 0.8 VDD - 0.8 -- -- -- 0.7VDD Typ(2) -- -- -- -- -- -- -- -- -- Max -- 0.1 -- -- 0.4 1 VDD V Unit V
V
V
VIL
VSS
--
0.2VDD
V
IDD
-- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- 12 22
12 3 4 2 10 20 1 5 1 12 8 -- --
mA mA mA mA A A A A
IIL IIN
-- --
COUT CIN CIN CIN
-- -- -- --
pF pF pF pF
(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switching currents inherent in CMOS designs (see Section 2). (2) Typical values are at mid point of voltage range and at 25C only. (3) RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 8.0MHz); all inputs 0.2 V from rail; no DC loads; maximum load on outputs 50pF (20pF on OSC2). STOP /WAIT IDD: all ports configured as inputs; VIL = 0.2 V and VIH = VDD - 0.2 V: STOP IDD measured with OSC1 = VDD. WAIT IDD is affected linearly by the OSC2 capacitance.
15
Freescale I-2
HIGH SPEED OPERATION
MC68HC05B6 Rev. 4.1
I.2
A/D converter characteristics
Table I-3 A/D characteristics for 5V operation
(VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = -40 to +85C) Characteristic Resolution Non-linearity Quantization error Parameter Number of bits resolved by the A/D Max deviation from the best straight line through the A/D transfer characteristics (VRH = VDD and VRL = 0V) Uncertainty due to converter resolution Min 8 -- -- -- VRL VRL VSS - 0.1 3 Max -- 0.5 0.5 1 VRH VDD + 0.1 VRH -- Unit Bit LSB LSB LSB V V V V
Difference between the actual input voltage and Absolute accuracy the full-scale equivalent of the binary code output code for all errors Conversion range VRH VR(1) Conversion time VRL Analog input voltage range Maximum analog reference voltage Minimum analog reference voltage Minimum difference between VRH and VRL Total time to perform a single analog to digital conversion a. External clock (OSC1, OSC2) b. Internal RC oscillator Conversion result never decreases with an increase in input voltage and has no missing codes
-- --
32 32 GUARANTEED
tCYC s
Monotonicity
Zero input reading Conversion result when VIN = VRL Full scale reading Conversion result when VIN = VRH Analog input acquisition sampling Sample acquisition a. External clock (OSC1, OSC2) time b. Internal RC oscillator(2) Sample/hold capacitance Input leakage(3) Input capacitance on PD0/AN0-PD7/AN7 Input leakage on A/D pins PD0/AN0-PD7/AN7 VRL, VRH
00 -- -- -- -- -- --
-- FF 12 12 12 1 1
Hex Hex tCYC s pF A A
(1) Performance verified down to 2.5V VR, but accuracy is tested and guaranteed at VR = 5V10%. (2) Source impedances greater than 10k will adversely affect internal charging time during input sampling. (3) The external system error caused by input leakage current is approximately equal to the product of R source and input current. Input current to A/D channel will be dependent on external source impedance (see Figure 8-2).
MC68HC05B6 Rev. 4.1
HIGH SPEED OPERATION
Freescale I-3
15
I.3
Control timing for 5V operation
(VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = -40 to +85C) Characteristic Frequency of operation Crystal option External clock option Internal operating frequency (fOSC/2) Crystal External clock Cycle time (see Figure 9-1) Crystal oscillator start-up time (see Figure 9-1) Stop recovery start-up time (crystal oscillator) External RESET input pulse width Power-on RESET output pulse width 4064 cycle 16 cycle Watchdog RESET output pulse width Watchdog time-out EEPROM byte erase time 0 to 70 (standard) - 40 to 85 (extended) EEPROM byte program time(1) 0 to 70 (standard) - 40 to 85 (extended) Timer (see Figure I-1) Resolution(2) Input capture pulse width Input capture pulse period Interrupt pulse width (edge-triggered) Interrupt pulse period OSC1 pulse width Write/Erase endurance(5)(6) Data retention(5)(6) Symbol fOSC fOSC fOP fOP tCYC tOXOV tILCH tRL tPORL tPORL tDOGL tDOG tERA tERA tPROG tPROG tRESL tTH, tTL tTLTL tILIH tILIL tOH, tOL -- -- 1.5 4064 16 1.5 6144 10 10 10 10 4 125 --(3) 125 --(4) 90 10000 10 Min -- dc -- dc 250 -- Max 8.0 8.0 4.0 4.0 -- 100 100 -- -- -- -- 7168 -- -- -- -- -- -- -- -- -- -- Unit MHz MHz MHz MHz ns ms ms tCYC tCYC tCYC tCYC tCYC ms ms ms ms tCYC ns tCYC ns tCYC ns cycles years
(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when programming the EEPROM. (2) Since a 2-bit prescaler in the timer must count four external cycles (tCYC), this is the limiting factor in determining the timer resolution. (3) The minimum period tTLTL should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 tCYC. (4) The minimum period tILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 tCYC. (5) At a temperature of 85C (6) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information.
15
Freescale I-4
HIGH SPEED OPERATION
MC68HC05B6 Rev. 4.1
tTLTL External signal (TCAP1, TCAP2)
tTH
tTL
Figure I-1 Timer relationship
MC68HC05B6 Rev. 4.1
HIGH SPEED OPERATION
Freescale I-5
15
THIS PAGE LEFT BLANK INTENTIONALLY
15
Freescale I-6
HIGH SPEED OPERATION
MC68HC05B6 Rev. 4.1
GLOSSARY
This section contains abbreviations and specialist words used in this data sheet and throughout the industry. Further information on many of the terms may be gleaned from Freescale's M68HC11 Reference Manual, M68HC11RM/AD, or from a variety of standard electronics text books.
$xxxx %xxxx A/D, ADC Bootstrap mode Byte CCR CERQUAD Clear CMOS COP CPU D/A, DAC EEPROM EPROM
The digits following the `$' are in hexadecimal format. The digits following the `%' are in binary format. Analog-to-digital (converter). In this mode the device automatically loads its internal memory from an external source on reset and then allows this program to be executed. Eight bits. Condition codes register; an integral part of the CPU. A ceramic package type, principally used for EPROM and high temperature devices. `0' -- the logic zero state; the opposite of `set'. Complementary metal oxide semiconductor. A semiconductor technology chosen for its low power consumption and good noise immunity. Computer operating properly. aka `watchdog'. This circuit is used to detect device runaway and provide a means for restoring correct operation. Central processing unit. Digital-to-analog (converter). Electrically erasable programmable read only memory. aka `EEROM'. Erasable programmable read only memory. This type of memory requires exposure to ultra-violet wavelengths in order to erase previous data. aka `PROM'. Electrostatic discharge. In this mode the internal address and data bus lines are connected to external pins. This enables the device to be used in much more complex systems, where there is a need for external memory for example.
ESD Expanded mode
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MC68HC05B6
GLOSSARY
Freescale i
EVS HCMOS I/O Input capture
Evaluation system. One of the range of platforms provided by Freescale for evaluation and emulation of their devices. High-density complementary metal oxide semiconductor. A semiconductor technology chosen for its low power consumption and good noise immunity. Input/output; used to describe a bidirectional pin or function. (IC) This is a function provided by the timing system, whereby an external event is `captured' by storing the value of a counter at the instant the event is detected. This refers to an asynchronous external event and the handling of it by the MCU. The external event is detected by the MCU and causes a predetermined action to occur. Interrupt request. The overline indicates that this is an active-low signal format. A kilo-byte (of memory); 1024 bytes. Liquid crystal display. Least significant byte. Freescale's family of 8-bit MCUs. Microcontroller unit. Interconnect bus. A single wire, medium speed serial communications protocol. Most significant byte. Half a byte; four bits. Non-return to zero. The opcode is a byte which identifies the particular instruction and operating mode to the CPU. See also: prebyte, operand. The operand is a byte containing information the CPU needs to execute a particular instruction. There may be from 0 to 3 operands associated with an opcode. See also: opcode, prebyte. (OC) This is a function provided by the timing system, whereby an external event is generated when an internal counter value matches a predefined value. Plastic leaded chip carrier package. Phase-locked loop circuit. This provides a method of frequency multiplication, to enable the use of a low frequency crystal in a high frequency circuit. This byte is sometimes required to qualify an opcode, in order to fully specify a particular instruction. See also: opcode, operand.
Interrupt
IRQ K byte LCD LSB M68HC05 MCU MI BUS MSB Nibble NRZ Opcode Operand
Output compare
PLCC PLL
Prebyte
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GLOSSARY
MC68HC05B6
Pull-down, pull-up These terms refer to resistors, sometimes internal to the device, which are permanently connected to either ground or VDD. PWM Pulse width modulation. This term is used to describe a technique where the width of the high and low periods of a waveform is varied, usually to enable a representation of an analog value. Quad flat pack package. Random access memory. Fast read and write, but contents are lost when the power is removed. Radio frequency interference. Real-time interrupt. Read-only memory. This type of memory is programmed during device manufacture and cannot subsequently be altered. A standard serial communications protocol. Successive approximation register. Serial communications interface. `1' -- the logic one state; the opposite of `clear'. An area in the central belt of Scotland, so called because of the concentration of semiconductor manufacturers and users found there. In this mode the device functions as a self contained unit, requiring only I/O devices to complete a system. Serial peripheral interface. This mode is intended for factory testing. Transistor-transistor logic. Universal asynchronous receiver transmitter. Voltage controlled oscillator. see `COP'. A means of connecting outputs together such that the resulting composite output state is the logical OR of the state of the individual outputs. Two bytes; 16 bits. Non-maskable interrupt request. The overline indicates that this has an active-low signal format.
QFP RAM RFI RTI ROM RS-232C SAR SCI Set Silicon glen Single chip mode SPI Test mode TTL UART VCO Watchdog Wired-OR Word XIRQ
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MC68HC05B6
GLOSSARY
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GLOSSARY
MC68HC05B6
INDEX
In this index numeric entries are placed first; page references in italics indicate that the reference is to a figure.
A
A/D converter block diagram 8-2 during STOP mode 8-6 during WAIT mode 8-6 operation 8-1 registers ADDATA 8-3 ADSTAT 8-4 PORTD 8-3 A/D converter characteristics 11-8, 11-9, E-24, E-25, F-22, F-23, H-25, H-26, I-3 A/D status/control register ADON 4-5 absolute maximum ratings 11-1 ADDATA - A/D result data register 8-3 ADON - A/D converter on 8-5 ADON - A/D converter on bit 4-5 ADRC - A/D RC oscillator control 8-4 ADSTAT ADON 8-5 ADRC 8-4 CH3-CH0 8-5 COCO 8-4 ADSTAT - A/D status/control register 8-4 alternate counter register 5-3 analog input 8-6
MC68HC705B32 H-4 MC68HC705B5 C-2 PLM system 7-1 programmable timer 5-2 SCI 6-2, 6-2 watchdog system 9-3 bootstrap mode C-8, E-10, H-12
C
ceramic resonator 2-11 CH3-CH0 - A/D channels 3, 2, 1 and 0 8-5 COCO - Conversion complete flag 8-4 control timing 11-10, 11-11, C-19, E-26, E-27, F-24, F-25, H-27, H-28, I-4 COP watchdog 9-3 during STOP mode 9-4 during WAIT mode 9-4 counter 5-1 counter register 5-3 CPHA - Clock phase 6-12 CPOL - Clock polarity 6-12 crystal 2-11
D
data direction registers DDRA, DDRB, DDRC 4-5 data format 6-5 DC electrical characteristics 11-2, 11-5, C-19, E-22, E-23, F-20, F-21, H-23, H-24, I-2
B
Baud rate register SCP1, SCP0 6-18 SCR2, SCR1, SCR0 6-19 SCT2, SCT1, SCT0 6-18 block diagrams MC68HC05B16 D-3 MC68HC05B32 G-2 MC68HC05B4 A-2 MC68HC05B8 B-2 MC68HC705B16 E-2 MC68HC705B16N F-2
E
E1ERA - EEPROM erase/programming bit 3-3, E-7, F-7, H-9 E1LAT - EEPROM programming latch enable 3-4 E1LAT - EEPROM programming latch enable bit E-7, F-7, H-10
MC68HC05B6
INDEX
Freescale v
E1PGM - EEPROM charge pump enable/disable 3-4, E-7, F-7, H-10 E6LAT - EPROM programming latch enable bit E-6, F-6, H-9 E6PGM - EPROM program enable bit E-6, F-6, H-9 ECLK - External clock output bit 4-3 EE1P - EEPROM protect bit E-9, F-9 EE1P - EEPROM protection bit H-12 EEPROM 3-1, 3-3 erase operation 3-5 programming operation 3-6 read operation 3-5 STOP mode 3-7 WAIT mode 3-7 EEPROM control register E1ERA 3-3 E1LAT 3-4 E1PGM 3-4 ECLK 3-3 EEPROM options register EE1P E-9, F-9 SEC E-9, F-9 EEPROM/ECLK control ECLK 4-3 ELAT - EPROM programming latch enable bit C-6 EPGM - EPROM programming bit C-6 EPP - EPROM protect C-7 EPPT - EPROM protect test bit C-6 EPROM 13-2, C-5, E-5, F-5 control register C-6, E-6, F-6 options register C-7 program operation E-5, F-6, H-8 programming operation C-5 read operation E-5, F-5, H-8 EPROM control register ELAT C-6 EPGM C-6 EPPT C-6 EPROM electrical characteristics E-28, F-26, H-29 EPROM registers C-6 EPROM/EEPROM/ECLK control register E1ERA E-7, F-7 E1LAT E-7, F-7 E1PGM E-7, F-7 E6LAT E-6, F-6 E6PGM E-6, F-6 external clock 2-12, D-4, E-5, F-5, G-2 external interrupt 9-7
I
I/O pin states 4-2 I/O port structure 4-2, 4-2 ICF1 - Input capture flag 1 5-6 ICF2 - Input capture flag 2 5-7 IDLE - Idle line detect flag 6-16 IEDG1 - Input edge 1 5-5 ILIE - Idle line interrupt enable 6-14 Input capture registers ICR1 5-7 ICR2 5-8 input/output programming 4-1 INTE - External interrupt enable 3-9, 9-9 interrupts priorities 9-6 SCI 9-10 SWI 9-6 INTP, INTN - External interrupt sensitivity options 3-9, 9-9 IRQ 9-7 IRQ sensitivity 9-9
L
LBCL - Last bit clock 6-13 low power modes SLOW 2-9 STOP 2-6 WAIT 2-8
M
M - Mode 6-11 Mask option register PBPD E-8, F-8, H-11 PCPD E-8, F-9, H-11 RTIM E-8, F-8, H-11 RWAT E-8, F-8, H-11 WWAT E-8, F-8, H-11 mask options MC68HC05B6 1-3 maskable hardware interrupts 9-7 maskset errata D-1, H-1 MC68HC05B16 D-1 block diagram D-3 memory map D-5 MC68HC05B32 G-1 block diagram G-2 memory map G-3 MC68HC05B4 block diagram A-2 memory map A-3 MC68HC05B6 block diagram 1-3 mask options 1-3 memory map 3-2 pinouts 12-1, 12-2, 12-3
F
FE - Framing error flag 6-17
H
high speed operation I-1
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INDEX
MC68HC05B6
MC68HC05B8 B-1 block diagram B-2 memory map B-3 MC68HC705B16 E-1 block diagram E-2 memory map E-3 MC68HC705B16N F-1 block diagram F-2 memory map F-3 MC68HC705B32 H-3 block diagram H-4 memory map H-5 MC68HC705B5 C-1 block diagram C-2 memory map C-3 mechanical dimensions 12-4, 12-5, 12-6 memory map MC68HC05B16 D-5 MC68HC05B32 G-3 MC68HC05B4 A-3 MC68HC05B6 3-2 MC68HC05B8 B-3 MC68HC705B16 E-3 MC68HC705B16N F-3 MC68HC705B32 H-5 MC68HC705B5 C-3 Miscellaneous register INTE 3-9, 9-9 INTP, INTN 3-9, 9-9 POR 3-9, 9-2 SFA 3-10, 7-3 SFB 3-10, 7-3 SM 2-9, 3-10, 7-3 WDOG 3-10, 9-4 modes of operation jump to any address 2-4 low power modes 2-6 single chip mode 2-1
PCPD C-8 RTIM C-7 RWAT C-7 WWAT C-7 OPTR - options register 3-6, C-7 EE1P - EEPROM protection bit 3-7 SEC - Security bit 3-7 OR - Overrun error flag 6-17 oscillator connections 2-12, D-4 Output compare registers OCR1 5-9 OCR2 5-10
P
parallel bootstrap E-13, E-19, F-13, H-16 PBPD - Port B pull-down E-8, F-8 PBPD - Port B pull-down resistors C-8 PCPD - Port C pull-down E-8, F-9 PCPD - Port C pull-down resistors C-8 pin configurations 12-1 pins IRQ 2-10 OSC1, OSC2 2-11 PA0-PA7, PB0-PB7, PC0-PC7 2-13 PD0/AN0-PD7/AN7 2-13 PLMA, PLMB 2-13 RDI, TDO 2-13 RESET 2-10, 9-3 SCLK 2-13 TCAP1 2-10 TCAP2 2-11 TCMP1, TCMP2 2-11 VDD, VSS 2-10 VPP1 2-13 VRH, VRL 2-13 PLCC 12-1 PLM 5-11 block diagram 7-1 clock selection 7-4 PLMA, PLMB 7-2 POR - Power-on reset bit 3-9, 9-2 port registers PORTA, PORTB 4-4 PORTC 4-4 PORTD 4-5 PORTD - Port D data register 8-3 ports A and B 4-2 C 4-3 D 4-3 power-on reset 9-2 programmable timer block diagram 5-2 Pulse 5-11 pulse length modulation 5-11 registers PLMA, PLMB 5-11
N
NF - Noise error flag 6-17 nonmaskable software interrupt 9-6
O
OCF1 - Output compare flag 2 5-6 OCF2 - Output compare flag 2 5-7 OCIE - Output compares interrupt enable 5-4 OLV1 - Output level 1 5-5 OLV2 - Output level 2 5-5 Options register SEC H-12 options register EE1P H-12 EPP C-7 PBPD C-8
MC68HC05B6
INDEX
Freescale vii
pulse length modulation registers PLMA, PLMB 5-11
Q
QFP 12-2
R
R8 - Receive data bit 8 6-11 RAM 3-1 RDI 6-6 RDRF - Receive data register full flag 6-16 RE - receiver enable 6-15 receive data in 6-6 receiver 6-3 register outline 3-8 registers 3-1 RESET 9-3, E-5, F-5 reset timing diagram 9-1 resets 9-1 RIE - receiver interrupt enable 6-14 ROM 3-1 RTIM - Reset time C-7, E-8, F-8 RVU 13-2 RWAT - Watchdog after reset C-7, E-8, F-8 RWU - receiver wake-up 6-15
S
SBK - Send break 6-15 SCI block diagram 6-2 receiver 6-3 sampling technique 6-7 synchronous transmission 6-9 transmitter 6-3 two-wire system 6-1 SCI interrupts 9-10 SCI registers BAUD 6-18 SCCR1 6-10 SCCR2 6-14 SCDR 6-10 SCSR 6-16 SCP1, SCP0 - Serial prescaler select bits 6-18 SCR2, SCR1, SCR0 - SCI rate select bits 6-19 SCT2, SCT1, SCT0 - SCI rate select bits 6-18 SDIP 12-3 SEC - Secure bit E-9, F-9, H-12 self-check mode A-5 self-check ROM 3-2 serial bootstrap E-16 Serial communications control register 1 6-10 CPHA 6-12 CPOL 6-12
LBCL 6-13 M 6-11 R8 6-11 T8 6-11 WAKE 6-11 Serial communications control register 2 ILIE 6-14 RE 6-15 RIE 6-14 RWU 6-15 SBK 6-15 TCIE 6-14 TE 6-14 TIE 6-14 Serial communications data register 6-10 Serial communications status register FE 6-17 IDLE 6-16 NF 6-17 OR 6-17 RDRF 6-16 TC 6-16 TDRE 6-16 serial RAM loader 2-2, F-16, H-19 SFA - Slow or fast mode selection for PLMA 3-10, 7-3 SFB - Slow or fast mode selection for PLMB 3-10, 7-3 single chip mode 2-1 SLOW 2-9 SM - Slow mode 3-10, 7-3 SM - slow mode selection bit 2-9 start bit detection 6-6 STOP 2-6, 3-7, 5-12, 6-21, 7-4, 8-6, 9-4
T
T8 - transmit data bit 8 6-11 TC - Transmit complete flag 6-16 TCIE - Transmit complete interrupt enable 6-14 TDO 6-8 TDRE - Transmit data register empty flag 6-16 TE - Transmitter enable 6-14 TIE - Transmit interrupt enable 6-14 Timer control register IEDG1 5-5 OCIE 5-4 OLV1 5-5 OLV2 5-5 TOIE 5-4 timer interrupts 9-10 timer state diagrams 5-12 Timer status register ICF1 5-6 ICF2 5-7 OCF1 5-6 OCF2 5-7 TOF 5-6 TOF - Timer overflow status flag 5-6 TOIE - Timer overflow interrupt enable 5-4 transmit data out 6-8
Freescale viii
INDEX
MC68HC05B6
transmitter 6-3 TSR - Timer status register 5-6
V
verification media 13-2
W
WAIT 2-8, 3-7, 5-12, 6-21, 7-4, 8-6, 9-4 WAKE - Wake-up mode select 6-11 wake-up address mark 6-6 idle line 6-6 receiver 6-5 WDOG - Watchdog enable/disable 3-10, 9-4 WWAT - Watchdog during WAIT mode C-7, E-8, F-8
MC68HC05B6
INDEX
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INDEX
MC68HC05B6
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INTRODUCTION MODES OF OPERATION AND PIN DESCRIPTIONS MEMORY AND REGISTERS INPUT/OUTPUT PORTS PROGRAMMABLE TIMER SERIAL COMMUNICATIONS INTERFACE PULSE LENGTH D/A CONVERTERS ANALOG TO DIGITAL CONVERTER RESETS AND INTERRUPTS CPU CORE AND INSTRUCTION SET ELECTRICAL SPECIFICATIONS MECHANICAL DATA ORDERING INFORMATION APPENDICES HIGH SPEED OPERATION
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INTRODUCTION MODES OF OPERATION AND PIN DESCRIPTIONS MEMORY AND REGISTERS INPUT/OUTPUT PORTS PROGRAMMABLE TIMER SERIAL COMMUNICATIONS INTERFACE PULSE LENGTH D/A CONVERTERS ANALOG TO DIGITAL CONVERTER RESETS AND INTERRUPTS CPU CORE AND INSTRUCTION SET ELECTRICAL SPECIFICATIONS MECHANICAL DATA ORDERING INFORMATION APPENDICES HIGH SPEED OPERATION
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